Use new syntax
[litex.git] / milkymist / lm32 / __init__.py
1 from migen.fhdl.structure import *
2 from migen.bus import wishbone
3
4 class Inst:
5 def __init__(self):
6 self.ibus = i = wishbone.Master("lm32i")
7 self.dbus = d = wishbone.Master("lm32d")
8 self.interrupt = Signal(BV(32))
9 self.ext_break = Signal()
10 self._inst = Instance("lm32_top",
11 [("I_ADR_O", i.adr_o),
12 ("I_DAT_O", i.dat_o),
13 ("I_SEL_O", i.sel_o),
14 ("I_CYC_O", i.cyc_o),
15 ("I_STB_O", i.stb_o),
16 ("I_WE_O", i.we_o),
17 ("I_CTI_O", i.cti_o),
18 ("I_LOCK_O", BV(1)),
19 ("I_BTE_O", i.bte_o),
20 ("D_ADR_O", d.adr_o),
21 ("D_DAT_O", d.dat_o),
22 ("D_SEL_O", d.sel_o),
23 ("D_CYC_O", d.cyc_o),
24 ("D_STB_O", d.stb_o),
25 ("D_WE_O", d.we_o),
26 ("D_CTI_O", d.cti_o),
27 ("D_LOCK_O", BV(1)),
28 ("D_BTE_O", d.bte_o)],
29 [("interrupt", self.interrupt),
30 #("ext_break", self.ext_break),
31 ("I_DAT_I", i.dat_i),
32 ("I_ACK_I", i.ack_i),
33 ("I_ERR_I", i.err_i),
34 ("I_RTY_I", BV(1)),
35 ("D_DAT_I", d.dat_i),
36 ("D_ACK_I", d.ack_i),
37 ("D_ERR_I", d.err_i),
38 ("D_RTY_I", BV(1))],
39 [],
40 "clk_i",
41 "rst_i",
42 "lm32")
43
44 def get_fragment(self):
45 comb = [
46 self._inst.ins["I_RTY_I"].eq(0),
47 self._inst.ins["D_RTY_I"].eq(0)
48 ]
49 return Fragment(comb=comb, instances=[self._inst])