1 from migen
.fhdl
.structure
import *
2 from migen
.bus
import wishbone
6 self
.ibus
= i
= wishbone
.Interface()
7 self
.dbus
= d
= wishbone
.Interface()
8 self
.interrupt
= Signal(BV(32))
9 self
.ext_break
= Signal()
10 self
._inst
= Instance("lm32_top",
11 Instance
.ClockPort("clk_i"),
12 Instance
.ResetPort("rst_i"),
14 Instance
.Input("interrupt", self
.interrupt
),
15 #Instance.Input("ext_break", self.ext_break),
17 Instance
.Output("I_ADR_O", BV(32)),
18 Instance
.Output("I_DAT_O", i
.dat_w
),
19 Instance
.Output("I_SEL_O", i
.sel
),
20 Instance
.Output("I_CYC_O", i
.cyc
),
21 Instance
.Output("I_STB_O", i
.stb
),
22 Instance
.Output("I_WE_O", i
.we
),
23 Instance
.Output("I_CTI_O", i
.cti
),
24 Instance
.Output("I_LOCK_O", BV(1)),
25 Instance
.Output("I_BTE_O", i
.bte
),
26 Instance
.Input("I_DAT_I", i
.dat_r
),
27 Instance
.Input("I_ACK_I", i
.ack
),
28 Instance
.Input("I_ERR_I", i
.err
),
29 Instance
.Input("I_RTY_I", BV(1)),
31 Instance
.Output("D_ADR_O", BV(32)),
32 Instance
.Output("D_DAT_O", d
.dat_w
),
33 Instance
.Output("D_SEL_O", d
.sel
),
34 Instance
.Output("D_CYC_O", d
.cyc
),
35 Instance
.Output("D_STB_O", d
.stb
),
36 Instance
.Output("D_WE_O", d
.we
),
37 Instance
.Output("D_CTI_O", d
.cti
),
38 Instance
.Output("D_LOCK_O", BV(1)),
39 Instance
.Output("D_BTE_O", d
.bte
),
40 Instance
.Input("D_DAT_I", d
.dat_r
),
41 Instance
.Input("D_ACK_I", d
.ack
),
42 Instance
.Input("D_ERR_I", d
.err
),
43 Instance
.Input("D_RTY_I", BV(1)))
45 def get_fragment(self
):
47 self
._inst
.get_io("I_RTY_I").eq(0),
48 self
._inst
.get_io("D_RTY_I").eq(0),
49 self
.ibus
.adr
.eq(self
._inst
.get_io("I_ADR_O")[2:]),
50 self
.dbus
.adr
.eq(self
._inst
.get_io("D_ADR_O")[2:])
52 return Fragment(comb
=comb
, instances
=[self
._inst
])