1 from migen
.fhdl
.structure
import *
2 from migen
.bus
import wishbone
6 self
.ibus
= i
= wishbone
.Interface()
7 self
.dbus
= d
= wishbone
.Interface()
8 self
.interrupt
= Signal(BV(32))
9 self
.ext_break
= Signal()
10 self
._inst
= Instance("lm32_top",
30 [("interrupt", self
.interrupt
),
31 #("ext_break", self.ext_break),
44 def get_fragment(self
):
46 self
._inst
.ins
["I_RTY_I"].eq(0),
47 self
._inst
.ins
["D_RTY_I"].eq(0),
48 self
.ibus
.adr
.eq(self
._inst
.outs
["I_ADR_O"][2:]),
49 self
.dbus
.adr
.eq(self
._inst
.outs
["D_ADR_O"][2:])
51 return Fragment(comb
=comb
, instances
=[self
._inst
])