milkymist/lm32/__init__.py

   1 from migen.fhdl.structure import *
   2 from migen.bus import wishbone
   3
   4 class LM32:
   5         def __init__(self):
   6                 self.ibus = i = wishbone.Interface()
   7                 self.dbus = d = wishbone.Interface()
   8                 self.interrupt = Signal(BV(32))
   9                 self.ext_break = Signal()
  10                 self._inst = Instance("lm32_top",
  11                         [("I_ADR_O", BV(32)),
  12                         ("I_DAT_O", i.dat_w),
  13                         ("I_SEL_O", i.sel),
  14                         ("I_CYC_O", i.cyc),
  15                         ("I_STB_O", i.stb),
  16                         ("I_WE_O", i.we),
  17                         ("I_CTI_O", i.cti),
  18                         ("I_LOCK_O", BV(1)),
  19                         ("I_BTE_O", i.bte),
  20                         ("D_ADR_O", BV(32)),
  21                         ("D_DAT_O", d.dat_w),
  22                         ("D_SEL_O", d.sel),
  23                         ("D_CYC_O", d.cyc),
  24                         ("D_STB_O", d.stb),
  25                         ("D_WE_O", d.we),
  26                         ("D_CTI_O", d.cti),
  27                         ("D_LOCK_O", BV(1)),
  28                         ("D_BTE_O", d.bte)],
  29
  30                         [("interrupt", self.interrupt),
  31                         #("ext_break", self.ext_break),
  32                         ("I_DAT_I", i.dat_r),
  33                         ("I_ACK_I", i.ack),
  34                         ("I_ERR_I", i.err),
  35                         ("I_RTY_I", BV(1)),
  36                         ("D_DAT_I", d.dat_r),
  37                         ("D_ACK_I", d.ack),
  38                         ("D_ERR_I", d.err),
  39                         ("D_RTY_I", BV(1))],
  40
  41                         clkport="clk_i",
  42                         rstport="rst_i")
  43
  44         def get_fragment(self):
  45                 comb = [
  46                         self._inst.ins["I_RTY_I"].eq(0),
  47                         self._inst.ins["D_RTY_I"].eq(0),
  48                         self.ibus.adr.eq(self._inst.outs["I_ADR_O"][2:]),
  49                         self.dbus.adr.eq(self._inst.outs["D_ADR_O"][2:])
  50                 ]
  51                 return Fragment(comb=comb, instances=[self._inst])