1 from migen
.fhdl
.structure
import *
2 from migen
.bank
.description
import *
3 from migen
.bank
.eventmanager
import *
4 from migen
.bank
import csrgen
5 from migen
.bus
import wishbone
10 def __init__(self
, address
):
12 self
.phy_tx_clk
= Signal()
13 self
.phy_tx_data
= Signal(BV(4))
14 self
.phy_tx_en
= Signal()
15 self
.phy_tx_er
= Signal()
16 self
.phy_rx_clk
= Signal()
17 self
.phy_rx_data
= Signal(BV(4))
18 self
.phy_dv
= Signal()
19 self
.phy_rx_er
= Signal()
20 self
.phy_col
= Signal()
21 self
.phy_crs
= Signal()
22 self
.phy_rst_n
= Signal()
25 self
._phy
_reset
= RegisterField("phy_reset", reset
=1)
26 self
._rx
_count
_0 = RegisterField("rx_count_0", _count_width
, access_bus
=READ_ONLY
, access_dev
=WRITE_ONLY
)
27 self
._rx
_count
_1 = RegisterField("rx_count_1", _count_width
, access_bus
=READ_ONLY
, access_dev
=WRITE_ONLY
)
28 self
._tx
_count
= RegisterField("tx_count", _count_width
, access_dev
=READ_WRITE
)
29 self
._tx
_start
= RegisterField("tx_start", access_bus
=WRITE_ONLY
)
30 regs
= [self
._phy
_reset
, self
._rx
_count
_0, self
._rx
_count
_1, self
._tx
_count
, self
._tx
_start
]
32 self
._rx
_event
_0 = EventSourcePulse()
33 self
._rx
_event
_1 = EventSourcePulse()
34 self
._tx
_event
= EventSourcePulse()
35 self
.events
= EventManager(self
._rx
_event
_0, self
._rx
_event
_1, self
._tx
_event
)
37 self
.bank
= csrgen
.Bank(regs
+ self
.events
.get_registers(), address
=address
)
38 self
.membus
= wishbone
.Interface()
40 def get_fragment(self
):
41 init
= Signal(reset
=1)
44 rx_pending_0
= self
._rx
_event
_0.pending
45 rx_pending_1
= self
._rx
_event
_1.pending
46 rx_pending_0_r
= Signal()
47 rx_pending_1_r
= Signal()
49 self
.phy_rst_n
.eq(~self
._phy
_reset
.field
.r
),
51 rx_ready_0
.eq(init |
(rx_pending_0_r
& ~rx_pending_0
)),
52 rx_ready_1
.eq(init |
(rx_pending_1_r
& ~rx_pending_1
)),
54 self
._tx
_count
.field
.w
.eq(0),
55 self
._tx
_count
.field
.we
.eq(self
._tx
_event
.trigger
)
59 rx_pending_0_r
.eq(rx_pending_0
),
60 rx_pending_1_r
.eq(rx_pending_1
)
64 Instance
.ClockPort("sys_clk"),
65 Instance
.ResetPort("sys_rst"),
67 Instance
.Output("rx_done_0", self
._rx
_event
_0.trigger
),
68 Instance
.Output("rx_count_0", self
._rx
_count
_0.field
.w
),
69 Instance
.Output("rx_done_1", self
._rx
_event
_1.trigger
),
70 Instance
.Output("rx_count_1", self
._rx
_count
_1.field
.w
),
71 Instance
.Input("rx_ready_0", rx_ready_0
),
72 Instance
.Input("rx_ready_1", rx_ready_1
),
74 Instance
.Input("tx_start", self
._tx
_start
.re
),
75 Instance
.Input("tx_count", self
._tx
_count
.field
.r
),
76 Instance
.Output("tx_done", self
._tx
_event
.trigger
),
78 Instance
.Input("wb_adr_i", self
.membus
.adr
),
79 Instance
.Input("wb_dat_i", self
.membus
.dat_w
),
80 Instance
.Input("wb_sel_i", self
.membus
.sel
),
81 Instance
.Input("wb_stb_i", self
.membus
.stb
),
82 Instance
.Input("wb_cyc_i", self
.membus
.cyc
),
83 Instance
.Input("wb_we_i", self
.membus
.we
),
84 Instance
.Output("wb_dat_o", self
.membus
.dat_r
),
85 Instance
.Output("wb_ack_o", self
.membus
.ack
),
87 Instance
.Output("phy_tx_data", self
.phy_tx_data
),
88 Instance
.Output("phy_tx_en", self
.phy_tx_en
),
89 Instance
.Output("phy_tx_er", self
.phy_tx_er
),
90 Instance
.Input("phy_tx_clk", self
.phy_tx_clk
),
91 Instance
.Input("phy_rx_clk", self
.phy_rx_clk
),
92 Instance
.Input("phy_rx_data", self
.phy_rx_data
),
93 Instance
.Input("phy_dv", self
.phy_dv
),
94 Instance
.Input("phy_rx_er", self
.phy_rx_er
),
95 Instance
.Input("phy_col", self
.phy_col
),
96 Instance
.Input("phy_crs", self
.phy_crs
))
98 return Fragment(comb
, sync
, instances
=inst
) \
99 + self
.events
.get_fragment() \
100 + self
.bank
.get_fragment()