1 from migen
.fhdl
.structure
import *
2 from migen
.bus
import dfi
5 def __init__(self
, a
, ba
, d
):
10 for name
, width
, l
in [
11 ("clk2x_270", 1, ins
),
13 ("clk4x_wr_strb", 1, ins
),
15 ("clk4x_rd_strb", 1, ins
),
17 ("sd_clk_out_p", 1, outs
),
18 ("sd_clk_out_n", 1, outs
),
23 ("sd_ras_n", 1, outs
),
24 ("sd_cas_n", 1, outs
),
26 ("sd_dq", d
//2, inouts
),
27 ("sd_dm", d
//16, outs
),
28 ("sd_dqs", d
//16, inouts
)
31 s
= Signal(BV(width
), name
=name
)
32 setattr(self
, name
, s
)
35 self
.dfi
= dfi
.Interface(a
, ba
, d
, 2)
36 ins
+= self
.dfi
.get_standard_names(True, False)
37 outs
+= self
.dfi
.get_standard_names(False, True)
39 self
._inst
= Instance("s6ddrphy",
50 def get_fragment(self
):
51 return Fragment(instances
=[self
._inst
])