1 from migen
.fhdl
.structure
import *
2 from migen
.bus
import dfi
5 def __init__(self
, a
, ba
, d
):
7 Instance
.Parameter("NUM_AD", a
),
8 Instance
.Parameter("NUM_BA", ba
),
9 Instance
.Parameter("NUM_D", d
),
10 Instance
.ClockPort("sys_clk")
12 for name
, width
, cl
in [
13 ("clk2x_270", 1, Instance
.Input
),
14 ("clk4x_wr", 1, Instance
.Input
),
15 ("clk4x_wr_strb", 1, Instance
.Input
),
16 ("clk4x_rd", 1, Instance
.Input
),
17 ("clk4x_rd_strb", 1, Instance
.Input
),
19 ("sd_clk_out_p", 1, Instance
.Output
),
20 ("sd_clk_out_n", 1, Instance
.Output
),
21 ("sd_a", a
, Instance
.Output
),
22 ("sd_ba", ba
, Instance
.Output
),
23 ("sd_cs_n", 1, Instance
.Output
),
24 ("sd_cke", 1, Instance
.Output
),
25 ("sd_ras_n", 1, Instance
.Output
),
26 ("sd_cas_n", 1, Instance
.Output
),
27 ("sd_we_n", 1, Instance
.Output
),
28 ("sd_dq", d
//2, Instance
.InOut
),
29 ("sd_dm", d
//16, Instance
.Output
),
30 ("sd_dqs", d
//16, Instance
.InOut
)
33 s
= Signal(BV(width
), name
=name
)
34 setattr(self
, name
, s
)
35 inst_items
.append(cl(name
, s
))
37 self
.dfi
= dfi
.Interface(a
, ba
, d
, 2)
38 inst_items
+= [Instance
.Input(name
, signal
)
39 for name
, signal
in self
.dfi
.get_standard_names(True, False)]
40 inst_items
+= [Instance
.Output(name
, signal
)
41 for name
, signal
in self
.dfi
.get_standard_names(False, True)]
43 self
._inst
= Instance("s6ddrphy", *inst_items
)
45 def get_fragment(self
):
46 return Fragment(instances
=[self
._inst
])