1 from migen
.fhdl
.structure
import *
2 from migen
.bus
import dfi
3 from migen
.bank
.description
import *
4 from migen
.bank
import csrgen
7 def __init__(self
, csr_address
, a
, ba
, d
):
17 "clk4x_wr_strb_right",
24 setattr(self
, name
, s
)
29 for name
, width
, l
in [
30 ("sd_clk_out_p", 1, outs
),
31 ("sd_clk_out_n", 1, outs
),
36 ("sd_ras_n", 1, outs
),
37 ("sd_cas_n", 1, outs
),
39 ("sd_dq", sd_d
, inouts
),
40 ("sd_dm", sd_d
//8, outs
),
41 ("sd_dqs", sd_d
//8, inouts
)
44 s
= Signal(BV(width
), name
=name
)
45 setattr(self
, name
, s
)
47 self
._sd
_pins
.append(s
)
49 self
.dfi
= dfi
.Interface(a
, ba
, d
)
50 ins
+= self
.dfi
.get_standard_names(True, False)
51 outs
+= self
.dfi
.get_standard_names(False, True)
59 ("cfg_regdimm", BV(1)),
65 ("diag_dq_recal", BV(1)),
66 ("diag_io_sel", BV(9)),
67 ("diag_disable_cal_on_startup", BV(1)),
68 ("diag_cal_bits", BV(2)),
69 ("diag_short_cal", BV(1))
72 ("phy_cal_done", BV(1)),
80 self
._inst
= Instance("spartan6_soft_phy",
89 ("DQ_IO_LOC", Constant(2**32-1, BV(32))),
90 ("DM_IO_LOC", Constant(2**4-1, BV(4)))
94 self
._reset
_n
= Field("reset_n")
95 self
._init
_done
= Field("init_done")
96 self
._phy
_cal
_done
= Field("phy_cal_done", 1, READ_ONLY
, WRITE_ONLY
)
97 self
._status
= RegisterFields("status",
98 [self
._reset
_n
, self
._init
_done
, self
._phy
_cal
_done
])
99 self
._req
= RegisterRaw("req", 2)
100 self
._req
_addr
= RegisterField("req_addr", 8, READ_ONLY
, WRITE_ONLY
)
102 self
.bank
= csrgen
.Bank([self
._status
, self
._req
, self
._req
_addr
],
105 def get_fragment(self
):
111 self
._inst
.ins
["cfg_al"].eq(0),
112 self
._inst
.ins
["cfg_cl"].eq(3),
113 self
._inst
.ins
["cfg_bl"].eq(1),
114 self
._inst
.ins
["cfg_regdimm"].eq(0),
116 self
._inst
.ins
["diag_dq_recal"].eq(0),
117 self
._inst
.ins
["diag_io_sel"].eq(0),
118 self
._inst
.ins
["diag_disable_cal_on_startup"].eq(0),
119 self
._inst
.ins
["diag_cal_bits"].eq(0),
120 self
._inst
.ins
["diag_short_cal"].eq(0),
122 self
._inst
.ins
["reset_n"].eq(self
._reset
_n
.r
),
123 self
._inst
.ins
["init_done"].eq(self
._init
_done
.r
),
124 self
._phy
_cal
_done
.w
.eq(self
._inst
.outs
["phy_cal_done"]),
125 self
._req
_addr
.field
.w
.eq(self
._inst
.outs
["cpg_addr"][2:10]),
127 self
._req
.w
.eq(Cat(pending_r
, pending_w
)),
128 cpg_busy
.eq(pending_r | pending_w
),
129 self
._inst
.ins
["cpg_busy"].eq(cpg_busy
)
132 If(self
._inst
.outs
["cpg_r_req"], pending_r
.eq(1)),
133 If(self
._inst
.outs
["cpg_w_req"], pending_w
.eq(1)),
134 If(self
._req
.re
& self
._req
.r
[0], pending_r
.eq(0)),
135 If(self
._req
.re
& self
._req
.r
[1], pending_w
.eq(0))
137 return Fragment(comb
, sync
, instances
=[self
._inst
], pads
=set(self
._sd
_pins
)) \
138 + self
.bank
.get_fragment()