Prepare for new DDR PHY
[litex.git] / milkymist / s6ddrphy / __init__.py
1 from migen.fhdl.structure import *
2 from migen.bus import dfi
3
4 class S6DDRPHY:
5 def __init__(self, a, ba, d):
6 ins = []
7 outs = []
8 inouts = []
9
10 for name in [
11 "clk2x_90",
12 "clk4x_wr",
13 "clk4x_wr_strb",
14 "clk4x_rd",
15 "clk4x_rd_strb"
16 ]:
17 s = Signal(name=name)
18 setattr(self, name, s)
19 ins.append((name, s))
20
21 self._sd_pins = []
22 for name, width, l in [
23 ("sd_clk_out_p", 1, outs),
24 ("sd_clk_out_n", 1, outs),
25 ("sd_a", a, outs),
26 ("sd_ba", ba, outs),
27 ("sd_cs_n", 1, outs),
28 ("sd_cke", 1, outs),
29 ("sd_ras_n", 1, outs),
30 ("sd_cas_n", 1, outs),
31 ("sd_we_n", 1, outs),
32 ("sd_dq", d//2, inouts),
33 ("sd_dm", d//16, outs),
34 ("sd_dqs", d//16, inouts)
35
36 ]:
37 s = Signal(BV(width), name=name)
38 setattr(self, name, s)
39 l.append((name, s))
40 self._sd_pins.append(s)
41
42 self.dfi = dfi.Interface(a, ba, d, 2)
43 ins += self.dfi.get_standard_names(True, False)
44 outs += self.dfi.get_standard_names(False, True)
45
46 self._inst = Instance("s6ddrphy",
47 outs,
48 ins,
49 inouts,
50 [
51 ("NUM_AD", a),
52 ("NUM_BA", ba),
53 ("NUM_D", d)
54 ],
55 clkport="sys_clk")
56
57 def get_fragment(self):
58 return Fragment(instances=[self._inst], pads=set(self._sd_pins))