1 from migen
.fhdl
.structure
import *
2 from migen
.bus
import dfi
5 def __init__(self
, a
, ba
, d
):
18 setattr(self
, name
, s
)
22 for name
, width
, l
in [
23 ("sd_clk_out_p", 1, outs
),
24 ("sd_clk_out_n", 1, outs
),
29 ("sd_ras_n", 1, outs
),
30 ("sd_cas_n", 1, outs
),
32 ("sd_dq", d
//2, inouts
),
33 ("sd_dm", d
//16, outs
),
34 ("sd_dqs", d
//16, inouts
)
37 s
= Signal(BV(width
), name
=name
)
38 setattr(self
, name
, s
)
40 self
._sd
_pins
.append(s
)
42 self
.dfi
= dfi
.Interface(a
, ba
, d
, 2)
43 ins
+= self
.dfi
.get_standard_names(True, False)
44 outs
+= self
.dfi
.get_standard_names(False, True)
46 self
._inst
= Instance("s6ddrphy",
57 def get_fragment(self
):
58 return Fragment(instances
=[self
._inst
], pads
=set(self
._sd
_pins
))