4 from migen
.fhdl
.structure
import *
5 from miscope
.host
.regs
import *
7 def write_b(uart
, data
):
8 uart
.write(pack('B',data
))
13 def __init__(self
, port
, baudrate
=115200, addrmap
=None, busword
=8, debug
=False):
15 self
.baudrate
= str(baudrate
)
17 self
.uart
= serial
.Serial(port
, baudrate
, timeout
=0.25)
18 self
.regs
= build_map(addrmap
, busword
, self
.read
, self
.write
)
21 self
.uart
.flushOutput()
24 self
.uart
.flushInput()
26 self
.regs
.uart2wb_sel
.write(1)
32 self
.regs
.uart2wb_sel
.write(0)
35 self
.uart
.flushOutput()
38 def read(self
, addr
, burst_length
=1):
39 self
.uart
.flushInput()
40 write_b(self
.uart
, self
.READ_CMD
)
41 write_b(self
.uart
, burst_length
)
43 write_b(self
.uart
, (addr
& 0xff000000) >> 24)
44 write_b(self
.uart
, (addr
& 0x00ff0000) >> 16)
45 write_b(self
.uart
, (addr
& 0x0000ff00) >> 8)
46 write_b(self
.uart
, (addr
& 0x000000ff))
48 for i
in range(burst_length
):
52 val |
= ord(self
.uart
.read())
54 print("RD %08X @ %08X" %(val
, (addr
+i
)*4))
61 def write(self
, addr
, data
):
62 if isinstance(data
, list):
63 burst_length
= len(data
)
66 write_b(self
.uart
, self
.WRITE_CMD
)
67 write_b(self
.uart
, burst_length
)
69 write_b(self
.uart
, (addr
& 0xff000000) >> 24)
70 write_b(self
.uart
, (addr
& 0x00ff0000) >> 16)
71 write_b(self
.uart
, (addr
& 0x0000ff00) >> 8)
72 write_b(self
.uart
, (addr
& 0x000000ff))
73 if isinstance(data
, list):
74 for i
in range(len(data
)):
77 write_b(self
.uart
, (dat
& 0xff000000) >> 24)
80 print("WR %08X @ %08X" %(data
[i
], (addr
+ i
)*4))
84 write_b(self
.uart
, (dat
& 0xff000000) >> 24)
87 print("WR %08X @ %08X" %(data
, (addr
* 4)))