revert submodules/specials/clock_domains syntax
[litex.git] / miscope / host / uart2wishbone.py
1 import string
2 import serial
3 from struct import *
4 from migen.fhdl.structure import *
5 from miscope.host.regs import *
6
7 def write_b(uart, data):
8 uart.write(pack('B',data))
9
10 class Uart2Wishbone:
11 WRITE_CMD = 0x01
12 READ_CMD = 0x02
13 def __init__(self, port, baudrate=115200, addrmap=None, busword=8, debug=False):
14 self.port = port
15 self.baudrate = str(baudrate)
16 self.debug = debug
17 self.uart = serial.Serial(port, baudrate, timeout=0.25)
18 self.regs = build_map(addrmap, busword, self.read, self.write)
19
20 def open(self):
21 self.uart.flushOutput()
22 self.uart.close()
23 self.uart.open()
24 self.uart.flushInput()
25 try:
26 self.regs.uart2wb_sel.write(1)
27 except:
28 pass
29
30 def close(self):
31 try:
32 self.regs.uart2wb_sel.write(0)
33 except:
34 pass
35 self.uart.flushOutput()
36 self.uart.close()
37
38 def read(self, addr, burst_length=1):
39 self.uart.flushInput()
40 write_b(self.uart, self.READ_CMD)
41 write_b(self.uart, burst_length)
42 addr = addr//4
43 write_b(self.uart, (addr & 0xff000000) >> 24)
44 write_b(self.uart, (addr & 0x00ff0000) >> 16)
45 write_b(self.uart, (addr & 0x0000ff00) >> 8)
46 write_b(self.uart, (addr & 0x000000ff))
47 values = []
48 for i in range(burst_length):
49 val = 0
50 for j in range(4):
51 val = val << 8
52 val |= ord(self.uart.read())
53 if self.debug:
54 print("RD %08X @ %08X" %(val, (addr+i)*4))
55 values.append(val)
56 if burst_length == 1:
57 return values[0]
58 else:
59 return values
60
61 def write(self, addr, data):
62 if isinstance(data, list):
63 burst_length = len(data)
64 else:
65 burst_length = 1
66 write_b(self.uart, self.WRITE_CMD)
67 write_b(self.uart, burst_length)
68 addr = addr//4
69 write_b(self.uart, (addr & 0xff000000) >> 24)
70 write_b(self.uart, (addr & 0x00ff0000) >> 16)
71 write_b(self.uart, (addr & 0x0000ff00) >> 8)
72 write_b(self.uart, (addr & 0x000000ff))
73 if isinstance(data, list):
74 for i in range(len(data)):
75 dat = data[i]
76 for j in range(4):
77 write_b(self.uart, (dat & 0xff000000) >> 24)
78 dat = dat << 8
79 if self.debug:
80 print("WR %08X @ %08X" %(data[i], (addr + i)*4))
81 else:
82 dat = data
83 for j in range(4):
84 write_b(self.uart, (dat & 0xff000000) >> 24)
85 dat = dat << 8
86 if self.debug:
87 print("WR %08X @ %08X" %(data, (addr * 4)))