break down sdram, improve consistency of core names
[litex.git] / misoc / cores / dvi_sampler / charsync.py
1 from migen import *
2 from migen.genlib.cdc import MultiReg
3 from migen.genlib.misc import optree
4 from migen.bank.description import *
5
6 from misoc.dvisampler.common import control_tokens
7
8
9 class CharSync(Module, AutoCSR):
10 def __init__(self, required_controls=8):
11 self.raw_data = Signal(10)
12 self.synced = Signal()
13 self.data = Signal(10)
14
15 self._char_synced = CSRStatus()
16 self._ctl_pos = CSRStatus(bits_for(9))
17
18 ###
19
20 raw_data1 = Signal(10)
21 self.sync.pix += raw_data1.eq(self.raw_data)
22 raw = Signal(20)
23 self.comb += raw.eq(Cat(raw_data1, self.raw_data))
24
25 found_control = Signal()
26 control_position = Signal(max=10)
27 self.sync.pix += found_control.eq(0)
28 for i in range(10):
29 self.sync.pix += If(optree("|", [raw[i:i+10] == t for t in control_tokens]),
30 found_control.eq(1),
31 control_position.eq(i)
32 )
33
34 control_counter = Signal(max=required_controls)
35 previous_control_position = Signal(max=10)
36 word_sel = Signal(max=10)
37 self.sync.pix += [
38 If(found_control & (control_position == previous_control_position),
39 If(control_counter == (required_controls - 1),
40 control_counter.eq(0),
41 self.synced.eq(1),
42 word_sel.eq(control_position)
43 ).Else(
44 control_counter.eq(control_counter + 1)
45 )
46 ).Else(
47 control_counter.eq(0)
48 ),
49 previous_control_position.eq(control_position)
50 ]
51 self.specials += MultiReg(self.synced, self._char_synced.status)
52 self.specials += MultiReg(word_sel, self._ctl_pos.status)
53
54 self.sync.pix += self.data.eq(raw >> word_sel)