misoclib/com/litepcie/example_designs/make.py

   1 #!/usr/bin/env python3
   2
   3 import sys
   4 import os
   5 import argparse
   6 import subprocess
   7 import struct
   8 import importlib
   9
  10 from mibuild.tools import write_to_file
  11 from migen.util.misc import autotype
  12 from migen.fhdl import verilog, edif
  13 from migen.fhdl.structure import _Fragment
  14 from migen.bank.description import CSRStatus
  15 from mibuild import tools
  16 from mibuild.xilinx.common import *
  17
  18 from misoclib.soc import cpuif
  19 from misoclib.com.litepcie.common import *
  20
  21
  22 def _import(default, name):
  23     return importlib.import_module(default + "." + name)
  24
  25
  26 def _get_args():
  27     parser = argparse.ArgumentParser(formatter_class=argparse.RawDescriptionHelpFormatter,
  28         description="""\
  29 LitePCIe - based on Migen.
  30
  31 This program builds and/or loads LitePCIe components.
  32 One or several actions can be specified:
  33
  34 clean           delete previous build(s).
  35 build-rtl       build verilog rtl.
  36 build-bitstream build-bitstream build FPGA bitstream.
  37 build-csr-csv   save CSR map into CSV file.
  38 build-csr-header save CSR map into C header file.
  39
  40 load-bitstream  load bitstream into volatile storage.
  41
  42 all             clean, build-csr-csv, build-bitstream, load-bitstream.
  43 """)
  44
  45     parser.add_argument("-t", "--target", default="dma", help="Core type to build")
  46     parser.add_argument("-s", "--sub-target", default="", help="variant of the Core type to build")
  47     parser.add_argument("-p", "--platform", default=None, help="platform to build for")
  48     parser.add_argument("-Ot", "--target-option", default=[], nargs=2, action="append", help="set target-specific option")
  49     parser.add_argument("-Op", "--platform-option", default=[], nargs=2, action="append", help="set platform-specific option")
  50     parser.add_argument("--csr_csv", default="./test/csr.csv", help="CSV file to save the CSR map into")
  51     parser.add_argument("--csr_header", default="../software/linux/kernel/csr.h", help="C header file to save the CSR map into")
  52     parser.add_argument("action", nargs="+", help="specify an action")
  53
  54     return parser.parse_args()
  55
  56 # Note: misoclib need to be installed as a python library
  57
  58 if __name__ == "__main__":
  59     args = _get_args()
  60
  61     # create top-level Core object
  62     target_module = _import("targets", args.target)
  63     if args.sub_target:
  64         top_class = getattr(target_module, args.sub_target)
  65     else:
  66         top_class = target_module.default_subtarget
  67
  68     if args.platform is None:
  69         platform_name = top_class.default_platform
  70     else:
  71         platform_name = args.platform
  72     platform_module = _import("mibuild.platforms", platform_name)
  73     platform_kwargs = dict((k, autotype(v)) for k, v in args.platform_option)
  74     platform = platform_module.Platform(**platform_kwargs)
  75
  76     build_name = top_class.__name__.lower() + "-" + platform_name
  77     top_kwargs = dict((k, autotype(v)) for k, v in args.target_option)
  78     soc = top_class(platform, **top_kwargs)
  79     soc.finalize()
  80     memory_regions = soc.get_memory_regions()
  81     csr_regions = soc.get_csr_regions()
  82
  83     # decode actions
  84     action_list = ["clean", "build-csr-csv", "build-csr-header", "build-bitstream", "load-bitstream", "all"]
  85     actions = {k: False for k in action_list}
  86     for action in args.action:
  87         if action in actions:
  88             actions[action] = True
  89         else:
  90             print("Unknown action: "+action+". Valid actions are:")
  91             for a in action_list:
  92                 print("  "+a)
  93             sys.exit(1)
  94
  95     print("""
  96       __   _ __      ___  _________
  97      / /  (_) /____ / _ \/ ___/  _/__
  98     / /__/ / __/ -_) ___/ /___/ // -_)
  99    /____/_/\__/\__/_/   \___/___/\__/
 100
 101   A small footprint and configurable PCIe
 102           core powered by Migen
 103 ====== Building options: ======
 104 Platform:  {}
 105 Target:    {}
 106 Subtarget: {}
 107 System Clk: {} MHz
 108 ===============================""".format(
 109     platform_name,
 110     args.target,
 111     top_class.__name__,
 112     soc.clk_freq/1000000
 113     )
 114 )
 115
 116     # dependencies
 117     if actions["all"]:
 118         actions["build-csr-csv"] = True
 119         actions["build-csr-header"] = True
 120         actions["build-bitstream"] = True
 121         actions["load-bitstream"] = True
 122
 123     if actions["build-bitstream"]:
 124         actions["build-csr-csv"] = True
 125         actions["build-csr-header"] = True
 126         actions["build-bitstream"] = True
 127         actions["load-bitstream"] = True
 128
 129     if actions["clean"]:
 130         subprocess.call(["rm", "-rf", "build/*"])
 131
 132     if actions["build-csr-csv"]:
 133         csr_csv = cpuif.get_csr_csv(csr_regions)
 134         write_to_file(args.csr_csv, csr_csv)
 135
 136     if actions["build-csr-header"]:
 137         csr_header = cpuif.get_csr_header(csr_regions, soc.get_constants(), with_access_functions=False)
 138         write_to_file(args.csr_header, csr_header)
 139
 140     if actions["build-bitstream"]:
 141         vns = platform.build(soc, build_name=build_name)
 142         if hasattr(soc, "do_exit") and vns is not None:
 143             if hasattr(soc.do_exit, '__call__'):
 144                 soc.do_exit(vns)
 145
 146     if actions["load-bitstream"]:
 147         prog = platform.create_programmer()
 148         prog.load_bitstream("build/" + build_name + platform.bitstream_ext)