misoclib/com/liteusb/example_designs/targets/simple.py

   1 from migen.genlib.io import CRG
   2 from migen.actorlib.fifo import SyncFIFO
   3
   4 from misoclib.soc import SoC
   5
   6 from misoclib.com.liteusb.common import *
   7 from misoclib.com.liteusb.phy.ft245 import FT245PHY
   8 from misoclib.com.liteusb.core import LiteUSBCore
   9 from misoclib.com.liteusb.frontend.wishbone import LiteUSBWishboneBridge
  10
  11 from misoclib.com.gpio import GPIOOut
  12
  13 class LiteUSBSoC(SoC):
  14     csr_map = {}
  15     csr_map.update(SoC.csr_map)
  16
  17     usb_map = {
  18         "bridge": 0
  19     }
  20
  21     def __init__(self, platform):
  22         clk_freq = int((1/(platform.default_clk_period))*1000000000)
  23         SoC.__init__(self, platform, clk_freq,
  24             cpu_type="none",
  25             with_csr=True, csr_data_width=32,
  26             with_uart=False,
  27             with_identifier=True,
  28             with_timer=False
  29         )
  30         self.submodules.crg = CRG(platform.request(platform.default_clk_name))
  31
  32         self.submodules.usb_phy = FT245PHY(platform.request("usb_fifo"), self.clk_freq)
  33         self.submodules.usb_core = LiteUSBCore(self.usb_phy, self.clk_freq, with_crc=False)
  34
  35
  36         # Wishbone Bridge
  37         usb_bridge_port = self.usb_core.crossbar.get_port(self.usb_map["bridge"])
  38         self.add_cpu_or_bridge(LiteUSBWishboneBridge(usb_bridge_port, self.clk_freq))
  39         self.add_wb_master(self.cpu_or_bridge.wishbone)
  40
  41         # Leds
  42         leds = Cat(iter([platform.request("user_led", i) for i in range(8)]))
  43         self.submodules.leds = GPIOOut(leds)
  44
  45 default_subtarget = LiteUSBSoC