liteusb: fix imports
[litex.git] / misoclib / com / liteusb / frontend / dma.py
1 from migen.fhdl.std import *
2 from migen.flow.actor import *
3 from migen.flow.network import *
4 from migen.actorlib import structuring, spi
5 from migen.bank.description import *
6 from migen.bank.eventmanager import *
7 from migen.genlib.record import Record
8
9 from misoclib.mem.sdram.frontend import dma_lasmi
10
11 from misoclib.com.liteusb.common import *
12
13 class FtdiDMAWriter(Module, AutoCSR):
14 def __init__(self, lasmim):
15 self.sink = sink = Sink(user_layout)
16
17 # Pack data
18 pack_factor = lasmim.dw//8
19 pack = structuring.Pack(phy_layout, pack_factor, reverse=True)
20 cast = structuring.Cast(pack.source.payload.layout, lasmim.dw)
21
22 # DMA
23 writer = dma_lasmi.Writer(lasmim)
24 self._reset = CSR()
25 self.dma = InsertReset(spi.DMAWriteController(writer, mode=spi.MODE_SINGLE_SHOT))
26 self.comb += self.dma.reset.eq(self._reset.r & self._reset.re)
27
28 # Remove sop/eop/length/dst fields from payload
29 self.comb += [
30 pack.sink.stb.eq(sink.stb),
31 pack.sink.payload.eq(sink.payload),
32 sink.ack.eq(pack.sink.ack)
33 ]
34
35 # Graph
36 g = DataFlowGraph()
37 g.add_pipeline(pack, cast, self.dma)
38 self.submodules += CompositeActor(g)
39
40 # IRQ
41 self.submodules.ev = EventManager()
42 self.ev.done = EventSourcePulse()
43 self.ev.finalize()
44 self.comb += self.ev.done.trigger.eq(sink.stb & sink.eop)
45
46 # CRC
47 self._crc_failed = CSRStatus()
48 self.sync += \
49 If(sink.stb & sink.eop,
50 self._crc_failed.status.eq(sink.error)
51 )
52
53 class FtdiDMAReader(Module, AutoCSR):
54 def __init__(self, lasmim, tag):
55 self.source = source = Source(user_layout)
56
57 reader = dma_lasmi.Reader(lasmim)
58 self.dma = spi.DMAReadController(reader, mode=spi.MODE_SINGLE_SHOT)
59
60 pack_factor = lasmim.dw//8
61 packed_dat = structuring.pack_layout(8, pack_factor)
62 cast = structuring.Cast(lasmim.dw, packed_dat)
63 unpack = structuring.Unpack(pack_factor, phy_layout, reverse=True)
64
65 # Graph
66 cnt = Signal(32)
67 self.sync += \
68 If(self.dma.generator._r_shoot.re,
69 cnt.eq(0)
70 ).Elif(source.stb & source.ack,
71 cnt.eq(cnt + 1)
72 )
73 g = DataFlowGraph()
74 g.add_pipeline(self.dma, cast, unpack)
75 self.submodules += CompositeActor(g)
76 self.comb += [
77 source.stb.eq(unpack.source.stb),
78 source.sop.eq(cnt == 0),
79 source.eop.eq(cnt == (self.dma.length*pack_factor-1)),
80 source.length.eq(self.dma.length*pack_factor+4),
81 source.d.eq(unpack.source.d),
82 source.dst.eq(tag),
83 unpack.source.ack.eq(source.ack)
84 ]
85
86 # IRQ
87 self.submodules.ev = EventManager()
88 self.ev.done = EventSourcePulse()
89 self.ev.finalize()
90 self.comb += self.ev.done.trigger.eq(source.stb & source.eop)
91
92 class FtdiDMA(Module, AutoCSR):
93 def __init__(self, lasmim_ftdi_dma_wr, lasmim_ftdi_dma_rd, tag):
94 self.tag = tag
95
96 self.submodules.writer = FtdiDMAWriter(lasmim_ftdi_dma_wr)
97 self.submodules.reader = FtdiDMAReader(lasmim_ftdi_dma_rd, self.tag)
98 self.submodules.ev = SharedIRQ(self.writer.ev, self.reader.ev)
99
100 self.sink = self.writer.sink
101 self.source = self.reader.source