3 from migen
.fhdl
.std
import *
4 from migen
.bank
.description
import *
5 from migen
.genlib
.misc
import optree
6 from migen
.genlib
.cdc
import MultiReg
8 class CounterADC(Module
, AutoCSR
):
9 def __init__(self
, charge
, sense
, width
=24):
10 if not isinstance(sense
, collections
.Iterable
):
15 self
._start
_busy
= CSR()
16 self
._overflow
= CSRStatus(channels
)
17 self
._polarity
= CSRStorage()
20 busy
= Signal(channels
)
23 for i
in range(channels
):
24 res
.append(CSRStatus(width
, name
="res"+str(i
)))
25 setattr(self
, "_res"+str(i
), res
[-1])
29 any_busy
.eq(optree("|",
30 [busy
[i
] for i
in range(channels
)])),
31 self
._start
_busy
.w
.eq(any_busy
)
37 If(self
._start
_busy
.re
,
39 busy
.eq((1 << channels
)-1),
40 self
._overflow
.status
.eq(0),
41 charge
.eq(~self
._polarity
.storage
)
43 Cat(count
, carry
).eq(count
+ 1),
45 self
._overflow
.status
.eq(busy
),
49 charge
.eq(self
._polarity
.storage
)
53 for i
in range(channels
):
54 sense_synced
= Signal()
55 self
.specials
+= MultiReg(sense
[i
], sense_synced
)
56 self
.sync
+= If(busy
[i
],
57 If(sense_synced
!= self
._polarity
.storage
,
58 res
[i
].status
.eq(count
),