remove stale programmer.py
[litex.git] / misoclib / counteradc / __init__.py
1 import collections
2
3 from migen.fhdl.std import *
4 from migen.bank.description import *
5 from migen.genlib.misc import optree
6 from migen.genlib.cdc import MultiReg
7
8 class CounterADC(Module, AutoCSR):
9 def __init__(self, charge, sense, width=24):
10 if not isinstance(sense, collections.Iterable):
11 sense = [sense]
12
13 channels = len(sense)
14
15 self._start_busy = CSR()
16 self._overflow = CSRStatus(channels)
17 self._polarity = CSRStorage()
18
19 count = Signal(width)
20 busy = Signal(channels)
21
22 res = []
23 for i in range(channels):
24 res.append(CSRStatus(width, name="res"+str(i)))
25 setattr(self, "_res"+str(i), res[-1])
26
27 any_busy = Signal()
28 self.comb += [
29 any_busy.eq(optree("|",
30 [busy[i] for i in range(channels)])),
31 self._start_busy.w.eq(any_busy)
32 ]
33
34 carry = Signal()
35
36 self.sync += [
37 If(self._start_busy.re,
38 count.eq(0),
39 busy.eq((1 << channels)-1),
40 self._overflow.status.eq(0),
41 charge.eq(~self._polarity.storage)
42 ).Elif(any_busy,
43 Cat(count, carry).eq(count + 1),
44 If(carry,
45 self._overflow.status.eq(busy),
46 busy.eq(0)
47 )
48 ).Else(
49 charge.eq(self._polarity.storage)
50 )
51 ]
52
53 for i in range(channels):
54 sense_synced = Signal()
55 self.specials += MultiReg(sense[i], sense_synced)
56 self.sync += If(busy[i],
57 If(sense_synced != self._polarity.storage,
58 res[i].status.eq(count),
59 busy[i].eq(0)
60 )
61 )