Minicon: small SDRAM controller
[litex.git] / misoclib / lasmicon / refresher.py
1 from migen.fhdl.std import *
2 from migen.genlib.misc import timeline
3 from migen.genlib.fsm import FSM
4
5 from misoclib.lasmicon.multiplexer import *
6
7 class Refresher(Module):
8 def __init__(self, a, ba, tRP, tREFI, tRFC):
9 self.req = Signal()
10 self.ack = Signal() # 1st command 1 cycle after assertion of ack
11 self.cmd = CommandRequest(a, ba)
12
13 ###
14
15 # Refresh sequence generator:
16 # PRECHARGE ALL --(tRP)--> AUTO REFRESH --(tRFC)--> done
17 seq_start = Signal()
18 seq_done = Signal()
19 self.sync += [
20 self.cmd.a.eq(2**10),
21 self.cmd.ba.eq(0),
22 self.cmd.cas_n.eq(1),
23 self.cmd.ras_n.eq(1),
24 self.cmd.we_n.eq(1),
25 seq_done.eq(0)
26 ]
27 self.sync += timeline(seq_start, [
28 (1, [
29 self.cmd.ras_n.eq(0),
30 self.cmd.we_n.eq(0)
31 ]),
32 (1+tRP, [
33 self.cmd.cas_n.eq(0),
34 self.cmd.ras_n.eq(0)
35 ]),
36 (1+tRP+tRFC, [
37 seq_done.eq(1)
38 ])
39 ])
40
41 # Periodic refresh counter
42 counter = Signal(max=tREFI)
43 start = Signal()
44 self.sync += [
45 start.eq(0),
46 If(counter == 0,
47 start.eq(1),
48 counter.eq(tREFI - 1)
49 ).Else(
50 counter.eq(counter - 1)
51 )
52 ]
53
54 # Control FSM
55 fsm = FSM()
56 self.submodules += fsm
57 fsm.act("IDLE", If(start, NextState("WAIT_GRANT")))
58 fsm.act("WAIT_GRANT",
59 self.req.eq(1),
60 If(self.ack,
61 seq_start.eq(1),
62 NextState("WAIT_SEQ")
63 )
64 )
65 fsm.act("WAIT_SEQ",
66 self.req.eq(1),
67 If(seq_done, NextState("IDLE"))
68 )