misoclib/mem/README

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   5
   6       Copyright 2014-2015 The University of Hong Kong
   7
   8         A small footprint and configurable SATA core
   9        developed for HKU by M-Labs Ltd & EnjoyDigital
  10
  11 [> Doc
  12 ---------
  13 HTML : www.enjoy-digital.fr/litex/litesata/
  14 PDF  : www.enjoy-digital.fr/litex/litesata.pdf
  15
  16 [> Intro
  17 ---------
  18 LiteSATA provides a small footprint and configurable SATA gen1/2/3 core.
  19
  20 LiteSATA is part of LiteX libraries whose aims are to lower entry level of complex
  21 FPGA cores by providing simple, elegant and efficient implementations of
  22 components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
  23
  24 The core uses simple and specific streaming buses and will provides in the future
  25 adapters to use standardized AXI or Avalon-ST streaming buses.
  26
  27 Since Python is used to describe the HDL, the core is highly and easily
  28 configurable.
  29
  30 The synthetizable BIST can be used as a starting point to integrate SATA in
  31 your own SoC.
  32
  33 LiteSATA uses technologies developed in partnership with M-Labs Ltd:
  34  - Migen enables generating HDL with Python in an efficient way.
  35  - MiSoC provides the basic blocks to build a powerful and small footprint SoC.
  36
  37 LiteSATA can be used as a Migen/MiSoC library (by simply installing  it
  38 with the provided setup.py) or can be integrated with your standard design flow
  39 by generating the verilog rtl that you will use as a standard core.
  40
  41 [> Features
  42 -----------
  43 PHY:
  44   - OOB, COMWAKE, COMINIT
  45   - ALIGN inserter/remover and bytes alignment on K28.5
  46   - 8B/10B encoding/decoding in transceiver
  47   - Errors detection and reporting
  48   - 32 bits interface
  49   - 1.5/3.0/6.0GBps supported speeds (respectively 37.5/75/150MHz system clk)
  50 Core:
  51   Link:
  52     - CONT inserter/remover
  53     - Scrambling/Descrambling of data
  54     - CRC inserter/checker
  55     - HOLD insertion/detection
  56     - Errors detection and reporting
  57   Transport/Command:
  58     - Easy to use user interfaces (Can be used with or without CPU)
  59     - 48 bits sector addressing
  60     - 3 supported commands: READ_DMA(_EXT), WRITE_DMA(_EXT), IDENTIFY_DEVICE
  61     - Errors detection and reporting
  62
  63 Frontend:
  64   - Configurable crossbar (simply use core.crossbar.get_port() to add a new port!)
  65   - Ports arbitration transparent to the user
  66   - Synthetizable BIST
  67
  68 [> Possibles improvements
  69 -------------------------
  70 - add standardized interfaces (AXI, Avalon-ST)
  71 - add NCQ support
  72 - add AES hardware encryption
  73 - add on-the-flow compression/decompression
  74 - add support for Altera PHYs.
  75 - add support for Lattice PHYs.
  76 - add support for Xilinx 7-Series GTP/GTH (currently only 7-Series GTX are
  77   supported)
  78 - add Zynq Linux drivers.
  79 - ... See below Support and consulting :)
  80
  81 If you want to support these features, please contact us at florent [AT]
  82 enjoy-digital.fr. You can also contact our partner on the public mailing list
  83 devel [AT] lists.m-labs.hk.
  84
  85
  86 [> Getting started
  87 ------------------
  88 1. Install Python3 and your vendor's software
  89
  90 2. Obtain Migen and install it:
  91   git clone https://github.com/m-labs/migen
  92   cd migen
  93   python3 setup.py install
  94   cd ..
  95
  96 Note: in case you have issues with Migen, please retry
  97 with our fork at:
  98   https://github.com/enjoy-digital/misoc
  99 until new features are merged.
 100
 101 3. Obtain LiteScope and install it:
 102   git clone https://github.com/enjoy-digital/litescope
 103   cd litescope
 104   python3 setup.py install
 105   cd ..
 106
 107 4. Obtain LiteSATA
 108   git clone https://github.com/enjoy-digital/litesata
 109
 110 5. Build and load BIST design (only for KC705 for now):
 111   python3 make.py all (-s BISTSoCDevel to add LiteScopeLA)
 112
 113 6. Test design (only for KC705 for now):
 114   go to ./test directory and run:
 115   change com port in config.py to your com port
 116   python3 bist.py
 117
 118 7. Visualize Link Layer transactions (if BISTSoCDevel):
 119   go to ./test directory and run:
 120   python3 test_la.py [your_cond]
 121   your_cond can be wr_cmd, id_cmd, rd_resp, ...
 122   (open test_la.py to see all conditions or add yours)
 123
 124 8. If you only want to build the core and use it with your
 125   regular design flow:
 126   python3 make.py -t core build-core
 127
 128 [> Simulations:
 129   Simulations are available in ./lib/sata/test:
 130     - crc_tb
 131     - scrambler_tb
 132     - phy_datapath_tb
 133     - link_tb
 134     - command_tb
 135     - bist_tb
 136   hdd.py is a simplified HDD model implementing all SATA layers.
 137   To run a simulation, move to ./lib/sata/test and run:
 138     make simulation_name
 139
 140 [> Tests :
 141   A synthetizable BIST is provided and can be controlled with ./test/bist.py
 142   By using LiteScope and the provided ./test/test_link.py example you are able to
 143   visualize the internal logic of the design and even inject the captured data in
 144   the HDD model!
 145
 146 [> License
 147 -----------
 148 LiteSATA is released under the very permissive two-clause BSD license. Under the
 149 terms of this license, you are authorized to use LiteSATA for closed-source
 150 proprietary designs.
 151 Even though we do not require you to do so, those things are awesome, so please
 152 do them if possible:
 153  - tell us that you are using LiteSATA
 154  - cite LiteSATA in publications related to research it has helped
 155  - send us feedback and suggestions for improvements
 156  - send us bug reports when something goes wrong
 157  - send us the modifications and improvements you have done to LiteSATA.
 158
 159 [> Support and consulting
 160 --------------------------
 161 We love open-source hardware and like sharing our designs with others.
 162
 163 LiteSATA is developed and maintained by EnjoyDigital.
 164
 165 If you would like to know more about LiteSATA or if you are already a happy user
 166 and would like to extend it for your needs, EnjoyDigital can provide standard
 167 commercial support as well as consulting services.
 168
 169 So feel free to contact us, we'd love to work with you! (and eventually shorten
 170 the list of the possible improvements :)
 171
 172 [> Contact
 173 E-mail: florent [AT] enjoy-digital.fr