misoclib/mor1kx/__init__.py

   1 from migen.fhdl.std import *
   2 from migen.bus import wishbone
   3
   4 class MOR1KX(Module):
   5         def __init__(self, reset_pc):
   6                 self.ibus = i = wishbone.Interface()
   7                 self.dbus = d = wishbone.Interface()
   8                 self.interrupt = Signal(32)
   9
  10                 ###
  11
  12                 i_adr_o = Signal(32)
  13                 d_adr_o = Signal(32)
  14                 self.specials += Instance("mor1kx",
  15                         p_FEATURE_INSTRUCTIONCACHE="ENABLED",
  16                         p_OPTION_ICACHE_BLOCK_WIDTH=4,
  17                         p_OPTION_ICACHE_SET_WIDTH=8,
  18                         p_OPTION_ICACHE_WAYS=1,
  19                         p_OPTION_ICACHE_LIMIT_WIDTH=31,
  20                         p_FEATURE_DATACACHE="ENABLED",
  21                         p_OPTION_DCACHE_BLOCK_WIDTH=4,
  22                         p_OPTION_DCACHE_SET_WIDTH=8,
  23                         p_OPTION_DCACHE_WAYS=1,
  24                         p_OPTION_DCACHE_LIMIT_WIDTH=31,
  25                         p_FEATURE_TIMER="NONE",
  26                         p_OPTION_PIC_TRIGGER="LEVEL",
  27                         p_FEATURE_SYSCALL="NONE",
  28                         p_FEATURE_TRAP="NONE",
  29                         p_FEATURE_RANGE="NONE",
  30                         p_FEATURE_OVERFLOW="NONE",
  31                         p_FEATURE_ADDC="NONE",
  32                         p_FEATURE_CMOV="NONE",
  33                         p_FEATURE_FFL1="NONE",
  34                         p_OPTION_CPU0="CAPPUCCINO",
  35                         p_OPTION_RESET_PC=reset_pc,
  36                         p_IBUS_WB_TYPE="B3_REGISTERED_FEEDBACK",
  37                         p_DBUS_WB_TYPE="B3_REGISTERED_FEEDBACK",
  38
  39                         i_clk=ClockSignal(),
  40                         i_rst=ResetSignal(),
  41
  42                         i_irq_i=self.interrupt,
  43
  44                         o_iwbm_adr_o=i_adr_o,
  45                         o_iwbm_dat_o=i.dat_w,
  46                         o_iwbm_sel_o=i.sel,
  47                         o_iwbm_cyc_o=i.cyc,
  48                         o_iwbm_stb_o=i.stb,
  49                         o_iwbm_we_o=i.we,
  50                         o_iwbm_cti_o=i.cti,
  51                         o_iwbm_bte_o=i.bte,
  52                         i_iwbm_dat_i=i.dat_r,
  53                         i_iwbm_ack_i=i.ack,
  54                         i_iwbm_err_i=i.err,
  55                         i_iwbm_rty_i=0,
  56
  57                         o_dwbm_adr_o=d_adr_o,
  58                         o_dwbm_dat_o=d.dat_w,
  59                         o_dwbm_sel_o=d.sel,
  60                         o_dwbm_cyc_o=d.cyc,
  61                         o_dwbm_stb_o=d.stb,
  62                         o_dwbm_we_o=d.we,
  63                         o_dwbm_cti_o=d.cti,
  64                         o_dwbm_bte_o=d.bte,
  65                         i_dwbm_dat_i=d.dat_r,
  66                         i_dwbm_ack_i=d.ack,
  67                         i_dwbm_err_i=d.err,
  68                         i_dwbm_rty_i=0)
  69
  70                 self.comb += [
  71                         self.ibus.adr.eq(i_adr_o[2:]),
  72                         self.dbus.adr.eq(d_adr_o[2:])
  73                 ]