2 parameter in_period = 0.0,
5 parameter clk2x_period = (in_period*f_div)/(2.0*f_mult)
14 output norflash_rst_n,
23 /* DDR off-chip clocking */
27 /* Base clock, buffered */
35 reg [19:0] rst_debounce;
36 always @(posedge sys_clk) begin
38 rst_debounce <= 20'hFFFFF;
39 else if(rst_debounce != 20'd0)
40 rst_debounce <= rst_debounce - 20'd1;
41 sys_rst <= rst_debounce != 20'd0;
44 initial rst_debounce <= 20'hFFFFF;
47 * We must release the Flash reset before the system reset
48 * because the Flash needs some time to come out of reset
49 * and the CPU begins fetching instructions from it
50 * as soon as the system reset is released.
51 * From datasheet, minimum reset pulse width is 100ns
52 * and reset-to-read time is 150ns.
55 reg [7:0] flash_rstcounter;
57 always @(posedge sys_clk) begin
59 flash_rstcounter <= 8'd0;
60 else if(~flash_rstcounter[7])
61 flash_rstcounter <= flash_rstcounter + 8'd1;
64 initial flash_rstcounter <= 8'd0;
66 assign norflash_rst_n = flash_rstcounter[7];
69 * Clock management. Inspired by the NWL reference design.
76 .IOSTANDARD("DEFAULT")
84 .DIVIDE_BYPASS("FALSE"),
103 .BANDWIDTH("OPTIMIZED"),
104 .CLKFBOUT_MULT(4*f_mult),
105 .CLKFBOUT_PHASE(0.0),
106 .CLKIN1_PERIOD(in_period),
107 .CLKIN2_PERIOD(in_period),
109 .CLKOUT0_DIVIDE(f_div),
110 .CLKOUT0_DUTY_CYCLE(0.5),
113 .CLKOUT1_DIVIDE(f_div),
114 .CLKOUT1_DUTY_CYCLE(0.5),
117 .CLKOUT2_DIVIDE(2*f_div),
118 .CLKOUT2_DUTY_CYCLE(0.5),
119 .CLKOUT2_PHASE(270.0),
121 .CLKOUT3_DIVIDE(4*f_div),
122 .CLKOUT3_DUTY_CYCLE(0.5),
125 .CLKOUT4_DIVIDE(4*f_mult),
126 .CLKOUT4_DUTY_CYCLE(0.5),
129 .CLKOUT5_DIVIDE(2*f_div),
130 .CLKOUT5_DUTY_CYCLE(0.5),
131 .CLKOUT5_PHASE(250.0),
133 .COMPENSATION("INTERNAL"),
136 .CLK_FEEDBACK("CLKFBOUT"),
137 .SIM_DEVICE("SPARTAN6")
140 .CLKFBOUT(buf_pll_fb_out),
141 .CLKOUT0(pllout0), /* < x4 clock for writes */
142 .CLKOUT1(pllout1), /* < x4 clock for reads */
143 .CLKOUT2(pllout2), /* < x2 270 clock for DQS, memory address and control signals */
144 .CLKOUT3(pllout3), /* < x1 clock for system and memory controller */
145 .CLKOUT4(pllout4), /* < buffered clk50 */
146 .CLKOUT5(pllout5), /* < x2 clock to off-chip DDR */
156 .CLKFBIN(buf_pll_fb_out),
177 .SERDESSTROBE(clk4x_wr_strb)
188 .SERDESSTROBE(clk4x_rd_strb)
219 .DDR_ALIGNMENT("NONE"),
233 .DDR_ALIGNMENT("NONE"),