misoclib/others/mxcrg/mxcrg.v

   1 module mxcrg #(
   2         parameter in_period = 0.0,
   3         parameter f_mult = 0,
   4         parameter f_div = 0,
   5         parameter clk2x_period = (in_period*f_div)/(2.0*f_mult)
   6 ) (
   7         input clk50_pad,
   8         input trigger_reset,
   9
  10         output sys_clk,
  11         output reg sys_rst,
  12
  13         /* Reset NOR flash */
  14         output norflash_rst_n,
  15
  16         /* DDR PHY clocks */
  17         output clk2x_270,
  18         output clk4x_wr,
  19         output clk4x_wr_strb,
  20         output clk4x_rd,
  21         output clk4x_rd_strb,
  22
  23         /* DDR off-chip clocking */
  24         output ddr_clk_pad_p,
  25         output ddr_clk_pad_n,
  26
  27         /* Base clock, buffered */
  28         output base50_clk
  29 );
  30
  31 /*
  32  * Reset
  33  */
  34
  35 reg [19:0] rst_debounce;
  36 always @(posedge sys_clk) begin
  37         if(trigger_reset)
  38                 rst_debounce <= 20'hFFFFF;
  39         else if(rst_debounce != 20'd0)
  40                 rst_debounce <= rst_debounce - 20'd1;
  41         sys_rst <= rst_debounce != 20'd0;
  42 end
  43
  44 initial rst_debounce <= 20'hFFFFF;
  45
  46 /*
  47  * We must release the Flash reset before the system reset
  48  * because the Flash needs some time to come out of reset
  49  * and the CPU begins fetching instructions from it
  50  * as soon as the system reset is released.
  51  * From datasheet, minimum reset pulse width is 100ns
  52  * and reset-to-read time is 150ns.
  53  */
  54
  55 reg [7:0] flash_rstcounter;
  56
  57 always @(posedge sys_clk) begin
  58         if(trigger_reset)
  59                 flash_rstcounter <= 8'd0;
  60         else if(~flash_rstcounter[7])
  61                 flash_rstcounter <= flash_rstcounter + 8'd1;
  62 end
  63
  64 initial flash_rstcounter <= 8'd0;
  65
  66 assign norflash_rst_n = flash_rstcounter[7];
  67
  68 /*
  69  * Clock management. Inspired by the NWL reference design.
  70  */
  71
  72 wire sdr_clk50;
  73 wire clkdiv;
  74
  75 IBUF #(
  76         .IOSTANDARD("DEFAULT")
  77 ) clk2_iob (
  78         .I(clk50_pad),
  79         .O(sdr_clk50)
  80 );
  81
  82 BUFIO2 #(
  83         .DIVIDE(1),
  84         .DIVIDE_BYPASS("FALSE"),
  85         .I_INVERT("FALSE")
  86 ) bufio2_inst2 (
  87         .I(sdr_clk50),
  88         .IOCLK(),
  89         .DIVCLK(clkdiv),
  90         .SERDESSTROBE()
  91 );
  92
  93 wire pll_lckd;
  94 wire buf_pll_fb_out;
  95 wire pllout0;
  96 wire pllout1;
  97 wire pllout2;
  98 wire pllout3;
  99 wire pllout4;
 100 wire pllout5;
 101
 102 PLL_ADV #(
 103         .BANDWIDTH("OPTIMIZED"),
 104         .CLKFBOUT_MULT(4*f_mult),
 105         .CLKFBOUT_PHASE(0.0),
 106         .CLKIN1_PERIOD(in_period),
 107         .CLKIN2_PERIOD(in_period),
 108
 109         .CLKOUT0_DIVIDE(f_div),
 110         .CLKOUT0_DUTY_CYCLE(0.5),
 111         .CLKOUT0_PHASE(0.0),
 112
 113         .CLKOUT1_DIVIDE(f_div),
 114         .CLKOUT1_DUTY_CYCLE(0.5),
 115         .CLKOUT1_PHASE(0.0),
 116
 117         .CLKOUT2_DIVIDE(2*f_div),
 118         .CLKOUT2_DUTY_CYCLE(0.5),
 119         .CLKOUT2_PHASE(270.0),
 120
 121         .CLKOUT3_DIVIDE(4*f_div),
 122         .CLKOUT3_DUTY_CYCLE(0.5),
 123         .CLKOUT3_PHASE(0.0),
 124
 125         .CLKOUT4_DIVIDE(4*f_mult),
 126         .CLKOUT4_DUTY_CYCLE(0.5),
 127         .CLKOUT4_PHASE(0.0),
 128
 129         .CLKOUT5_DIVIDE(2*f_div),
 130         .CLKOUT5_DUTY_CYCLE(0.5),
 131         .CLKOUT5_PHASE(250.0),
 132
 133         .COMPENSATION("INTERNAL"),
 134         .DIVCLK_DIVIDE(1),
 135         .REF_JITTER(0.100),
 136         .CLK_FEEDBACK("CLKFBOUT"),
 137         .SIM_DEVICE("SPARTAN6")
 138 ) pll (
 139         .CLKFBDCM(),
 140         .CLKFBOUT(buf_pll_fb_out),
 141         .CLKOUT0(pllout0), /* < x4 clock for writes */
 142         .CLKOUT1(pllout1), /* < x4 clock for reads */
 143         .CLKOUT2(pllout2), /* < x2 270 clock for DQS, memory address and control signals */
 144         .CLKOUT3(pllout3), /* < x1 clock for system and memory controller */
 145         .CLKOUT4(pllout4), /* < buffered clk50 */
 146         .CLKOUT5(pllout5), /* < x2 clock to off-chip DDR */
 147         .CLKOUTDCM0(),
 148         .CLKOUTDCM1(),
 149         .CLKOUTDCM2(),
 150         .CLKOUTDCM3(),
 151         .CLKOUTDCM4(),
 152         .CLKOUTDCM5(),
 153         .DO(),
 154         .DRDY(),
 155         .LOCKED(pll_lckd),
 156         .CLKFBIN(buf_pll_fb_out),
 157         .CLKIN1(clkdiv),
 158         .CLKIN2(1'b0),
 159         .CLKINSEL(1'b1),
 160         .DADDR(5'b00000),
 161         .DCLK(1'b0),
 162         .DEN(1'b0),
 163         .DI(16'h0000),
 164         .DWE(1'b0),
 165         .RST(1'b0),
 166         .REL(1'b0)
 167 );
 168
 169 BUFPLL #(
 170         .DIVIDE(4)
 171 ) wr_bufpll (
 172         .PLLIN(pllout0),
 173         .GCLK(sys_clk),
 174         .LOCKED(pll_lckd),
 175         .IOCLK(clk4x_wr),
 176         .LOCK(),
 177         .SERDESSTROBE(clk4x_wr_strb)
 178 );
 179
 180 BUFPLL #(
 181         .DIVIDE(4)
 182 ) rd_bufpll (
 183         .PLLIN(pllout1),
 184         .GCLK(sys_clk),
 185         .LOCKED(pll_lckd),
 186         .IOCLK(clk4x_rd),
 187         .LOCK(),
 188         .SERDESSTROBE(clk4x_rd_strb)
 189 );
 190
 191 BUFG bufg_x2_2(
 192         .I(pllout2),
 193         .O(clk2x_270)
 194 );
 195
 196 BUFG bufg_x1(
 197         .I(pllout3),
 198         .O(sys_clk)
 199 );
 200
 201 wire base50_clk;
 202 BUFG bufg_50(
 203         .I(pllout4),
 204         .O(base50_clk)
 205 );
 206
 207 wire clk2x_off;
 208 BUFG bufg_x2_offclk(
 209         .I(pllout5),
 210         .O(clk2x_off)
 211 );
 212
 213
 214 /*
 215  * SDRAM clock
 216  */
 217
 218 ODDR2 #(
 219         .DDR_ALIGNMENT("NONE"),
 220         .INIT(1'b0),
 221         .SRTYPE("SYNC")
 222 ) sd_clk_forward_p (
 223         .Q(ddr_clk_pad_p),
 224         .C0(clk2x_off),
 225         .C1(~clk2x_off),
 226         .CE(1'b1),
 227         .D0(1'b1),
 228         .D1(1'b0),
 229         .R(1'b0),
 230         .S(1'b0)
 231 );
 232 ODDR2 #(
 233         .DDR_ALIGNMENT("NONE"),
 234         .INIT(1'b0),
 235         .SRTYPE("SYNC")
 236 ) sd_clk_forward_n (
 237         .Q(ddr_clk_pad_n),
 238         .C0(clk2x_off),
 239         .C1(~clk2x_off),
 240         .CE(1'b1),
 241         .D0(1'b0),
 242         .D1(1'b1),
 243         .R(1'b0),
 244         .S(1'b0)
 245 );
 246
 247 endmodule