openpower/isa/av.mdwn

   1 <!-- DRAFT Instructions for PowerISA Version 3.0 B Book 1 -->
   2 <!-- https://libre-soc.org/openpower/sv/bitmanip/ -->
   3 <!-- https://libre-soc.org/openpower/sv/av_opcodes/ -->
   4
   5 # DRAFT Minimum/Maximum (Rc=1)
   6
   7 MM-Form
   8
   9 * minmax. RT,RA,RB,MMM (Rc=1)
  10
  11 Pseudo-code:
  12
  13 [[!inline pagenames="openpower/isa/av/minmax." raw="yes"]]
  14
  15 Special Registers Altered:
  16
  17     CR0                     (if Rc=1)
  18
  19 # DRAFT Minimum/Maximum
  20
  21 MM-Form
  22
  23 * minmax RT,RA,RB,MMM (Rc=0)
  24
  25 Pseudo-code:
  26
  27     a <- (RA|0)
  28     b <- (RB)
  29     if MMM[0] then  # word mode
  30         # shift left by XLEN/2 to make the dword comparison
  31         # do word comparison of the original inputs
  32         a <- a[XLEN/2:XLEN-1] || [0] * XLEN/2
  33         b <- b[XLEN/2:XLEN-1] || [0] * XLEN/2
  34     if MMM[1] then  # signed mode
  35         # invert sign bits to make the unsigned comparison
  36         # do signed comparison of the original inputs
  37         a[0] <- ¬a[0]
  38         b[0] <- ¬b[0]
  39     # if Rc = 1 then store the result of comparing a and b to CR0
  40     # if Rc = 1 then
  41     #     if a <u b then
  42     #         CR0 <- 0b100 || XER[SO]
  43     #     if a = b then
  44     #         CR0 <- 0b001 || XER[SO]
  45     #     if a >u b then
  46     #         CR0 <- 0b010 || XER[SO]
  47     if MMM[2] then  # max mode
  48         # swap a and b to make the less than comparison do
  49         # greater than comparison of the original inputs
  50         t <- a
  51         a <- b
  52         b <- t
  53     # store the entire selected source (even in word mode)
  54     # if Rc = 1 then store the result of comparing a and b to CR0
  55     if a <u b then RT <- (RA|0)
  56     else RT <- (RB)
  57
  58 Special Registers Altered:
  59
  60     None
  61
  62 # DRAFT Average Add
  63
  64 X-Form
  65
  66 * avgadd  RT,RA,RB (Rc=0)
  67 * avgadd. RT,RA,RB (Rc=1)
  68
  69 Pseudo-code:
  70
  71     a <- [0] * (XLEN+1)
  72     b <- [0] * (XLEN+1)
  73     a[1:XLEN] <- (RA)
  74     b[1:XLEN] <- (RB)
  75     r <- (a + b + 1)
  76     RT <- r[0:XLEN-1]
  77
  78 Special Registers Altered:
  79
  80     CR0                     (if Rc=1)
  81
  82 # DRAFT Absolute Signed Difference
  83
  84 X-Form
  85
  86 * absds  RT,RA,RB (Rc=0)
  87 * absds. RT,RA,RB (Rc=1)
  88
  89 Pseudo-code:
  90
  91     if (RA) < (RB) then RT <- ¬(RA) + (RB) + 1
  92     else                RT <- ¬(RB) + (RA) + 1
  93
  94 Special Registers Altered:
  95
  96     CR0                     (if Rc=1)
  97
  98 # DRAFT Absolute Unsigned Difference
  99
 100 X-Form
 101
 102 * absdu  RT,RA,RB (Rc=0)
 103 * absdu. RT,RA,RB (Rc=1)
 104
 105 Pseudo-code:
 106
 107     if (RA) <u (RB) then RT <- ¬(RA) + (RB) + 1
 108     else                RT <- ¬(RB) + (RA) + 1
 109
 110 Special Registers Altered:
 111
 112     CR0                     (if Rc=1)
 113
 114 # DRAFT Absolute Accumulate Unsigned Difference
 115
 116 X-Form
 117
 118 * absdacu  RT,RA,RB (Rc=0)
 119 * absdacu. RT,RA,RB (Rc=1)
 120
 121 Pseudo-code:
 122
 123     if (RA) <u (RB) then r <- ¬(RA) + (RB) + 1
 124     else                 r <- ¬(RB) + (RA) + 1
 125     RT <- (RT) + r
 126
 127 Special Registers Altered:
 128
 129     CR0                     (if Rc=1)
 130
 131 # DRAFT Absolute Accumulate Signed Difference
 132
 133 X-Form
 134
 135 * absdacs  RT,RA,RB (Rc=0)
 136 * absdacs. RT,RA,RB (Rc=1)
 137
 138 Pseudo-code:
 139
 140     if (RA) < (RB) then r <- ¬(RA) + (RB) + 1
 141     else                r <- ¬(RB) + (RA) + 1
 142     RT <- (RT) + r
 143
 144 Special Registers Altered:
 145
 146     CR0                     (if Rc=1)
 147
 148 # Carry Propagate
 149
 150 X-Form
 151
 152 * cprop RT,RA,RB (Rc=0)
 153 * cprop. RT,RA,RB (Rc=1)
 154
 155 Pseudo-code:
 156
 157     P <- (RA)
 158     G <- (RB)
 159     temp <- (P|G)+G
 160     RT <- temp^P
 161
 162 Special Registers Altered:
 163
 164     CR0                    (if Rc=1)
 165
 166 # DRAFT Bitmanip Masked
 167
 168 BM2-Form
 169
 170 * bmask  RT,RA,RB,bm,L
 171
 172 Pseudo-code:
 173
 174     if _RB = 0 then mask <- [1] * XLEN
 175     else mask <- (RB)
 176     ra <- (RA) & mask
 177     a1 <- ra
 178     if bm[4] = 0 then a1 <- ¬ra
 179     mode2 <- bm[2:3]
 180     if mode2 = 0 then a2 <- (¬ra)+1
 181     if mode2 = 1 then a2 <- ra-1
 182     if mode2 = 2 then a2 <- ra+1
 183     if mode2 = 3 then a2 <- ¬(ra+1)
 184     a1 <- a1 & mask
 185     a2 <- a2 & mask
 186     # select operator
 187     mode3 <- bm[0:1]
 188     if mode3 = 0 then result <- a1 | a2
 189     if mode3 = 1 then result <- a1 & a2
 190     if mode3 = 2 then result <- a1 ^ a2
 191     if mode3 = 3 then result <- undefined([0]*XLEN)
 192     result <- result & mask
 193     # optionally restore masked-out bits
 194     if L = 1 then
 195         result <- result | (RA & ¬mask)
 196     RT <- result
 197
 198 Special Registers Altered:
 199
 200     None
 201
 202 # Load Floating-Point Immediate
 203
 204 DX-Form
 205
 206 * fmvis FRS,D
 207
 208 Pseudo-code:
 209
 210     bf16 <- d0 || d1 || d2
 211     fp32 <- bf16 || [0]*16
 212     FRS  <- DOUBLE(fp32)
 213
 214 Special Registers Altered:
 215
 216     None
 217
 218 # Float Replace Lower-Half Single, Immediate
 219
 220 DX-Form
 221
 222 * fishmv FRS,D
 223
 224 Pseudo-code:
 225
 226     fp32 <- SINGLE((FRS))
 227     fp32[16:31] <- d0 || d1 || d2
 228     FRS <- DOUBLE(fp32)
 229
 230 Special Registers Altered:
 231
 232     None