openpower/isa/av.mdwn

   1 <!-- DRAFT Instructions for PowerISA Version 3.0 B Book 1 -->
   2 <!-- https://libre-soc.org/openpower/sv/bitmanip/ -->
   3 <!-- https://libre-soc.org/openpower/sv/av_opcodes/ -->
   4
   5 # DRAFT Fixed Point Signed Max (Rc=1)
   6
   7 X-Form
   8
   9 * maxs. RT,RA,RB (Rc=1)
  10
  11 Pseudo-code:
  12
  13     a <- (RA)
  14     b <- (RB)
  15     if   a > b then RT <- a
  16     else            RT <- b
  17     if      a < b then c <-  0b100
  18     else if a > b then c <-  0b010
  19     else               c <-  0b001
  20     CR0 <-  c || XER[SO]
  21
  22 Special Registers Altered:
  23
  24     CR0                     (if Rc=1)
  25
  26 # DRAFT Fixed Point Signed Max
  27
  28 X-Form
  29
  30 * maxs  RT,RA,RB (Rc=0)
  31
  32 Pseudo-code:
  33
  34     if   (RA) > (RB) then RT <- (RA)
  35     else                  RT <- (RB)
  36
  37 Special Registers Altered:
  38
  39     None
  40
  41 # DRAFT Fixed Point Unsigned Max
  42
  43 X-Form
  44
  45 * maxu  RT,RA,RB (Rc=0)
  46 * maxu. RT,RA,RB (Rc=1)
  47
  48 Pseudo-code:
  49
  50     if   (RA) >u (RB) then RT <- (RA)
  51     else                   RT <- (RB)
  52
  53 Special Registers Altered:
  54
  55     CR0                     (if Rc=1)
  56
  57 # DRAFT Fixed Point Signed Min
  58
  59 X-Form
  60
  61 * mins  RT,RA,RB (Rc=0)
  62 * mins. RT,RA,RB (Rc=1)
  63
  64 Pseudo-code:
  65
  66     if   (RA) < (RB) then RT <- (RA)
  67     else                  RT <- (RB)
  68
  69 Special Registers Altered:
  70
  71     CR0                     (if Rc=1)
  72
  73 # DRAFT Fixed Point Unsigned Min
  74
  75 X-Form
  76
  77 * minu  RT,RA,RB (Rc=0)
  78 * minu. RT,RA,RB (Rc=1)
  79
  80 Pseudo-code:
  81
  82     if   (RA) <u (RB) then RT <- (RA)
  83     else                   RT <- (RB)
  84
  85 Special Registers Altered:
  86
  87     CR0                     (if Rc=1)
  88
  89 # DRAFT Average Add
  90
  91 X-Form
  92
  93 * avgadd  RT,RA,RB (Rc=0)
  94 * avgadd. RT,RA,RB (Rc=1)
  95
  96 Pseudo-code:
  97
  98     a <- [0] * (XLEN+1)
  99     b <- [0] * (XLEN+1)
 100     a[1:XLEN] <- (RA)
 101     b[1:XLEN] <- (RB)
 102     r <- (a + b + 1)
 103     RT <- r[0:XLEN-1]
 104
 105 Special Registers Altered:
 106
 107     CR0                     (if Rc=1)
 108
 109 # DRAFT Absolute Signed Difference
 110
 111 X-Form
 112
 113 * absds  RT,RA,RB (Rc=0)
 114 * absds. RT,RA,RB (Rc=1)
 115
 116 Pseudo-code:
 117
 118     if (RA) < (RB) then RT <- ¬(RA) + (RB) + 1
 119     else                RT <- ¬(RB) + (RA) + 1
 120
 121 Special Registers Altered:
 122
 123     CR0                     (if Rc=1)
 124
 125 # DRAFT Absolute Unsigned Difference
 126
 127 X-Form
 128
 129 * absdu  RT,RA,RB (Rc=0)
 130 * absdu. RT,RA,RB (Rc=1)
 131
 132 Pseudo-code:
 133
 134     if (RA) <u (RB) then RT <- ¬(RA) + (RB) + 1
 135     else                RT <- ¬(RB) + (RA) + 1
 136
 137 Special Registers Altered:
 138
 139     CR0                     (if Rc=1)
 140
 141 # DRAFT Absolute Accumulate Unsigned Difference
 142
 143 X-Form
 144
 145 * absdacu  RT,RA,RB (Rc=0)
 146 * absdacu. RT,RA,RB (Rc=1)
 147
 148 Pseudo-code:
 149
 150     if (RA) <u (RB) then r <- ¬(RA) + (RB) + 1
 151     else                 r <- ¬(RB) + (RA) + 1
 152     RT <- (RT) + r
 153
 154 Special Registers Altered:
 155
 156     CR0                     (if Rc=1)
 157
 158 # DRAFT Absolute Accumulate Signed Difference
 159
 160 X-Form
 161
 162 * absdacs  RT,RA,RB (Rc=0)
 163 * absdacs. RT,RA,RB (Rc=1)
 164
 165 Pseudo-code:
 166
 167     if (RA) < (RB) then r <- ¬(RA) + (RB) + 1
 168     else                r <- ¬(RB) + (RA) + 1
 169     RT <- (RT) + r
 170
 171 Special Registers Altered:
 172
 173     CR0                     (if Rc=1)
 174
 175 # Carry Propagate
 176
 177 X-Form
 178
 179 * cprop RT,RA,RB (Rc=0)
 180 * cprop. RT,RA,RB (Rc=1)
 181
 182 Pseudo-code:
 183
 184     P <- (RA)
 185     G <- (RB)
 186     temp <- (P|G)+G
 187     RT <- temp^P
 188
 189 Special Registers Altered:
 190
 191     CR0                    (if Rc=1)
 192
 193 # DRAFT Bitmanip Masked
 194
 195 BM2-Form
 196
 197 * bmask  RT,RA,RB,bm,L
 198
 199 Pseudo-code:
 200
 201     if _RB = 0 then mask <- [1] * XLEN
 202     else mask <- (RB)
 203     ra <- (RA) & mask
 204     a1 <- ra
 205     if bm[4] = 0 then a1 <- ¬ra
 206     mode2 <- bm[2:3]
 207     if mode2 = 0 then a2 <- (¬ra)+1
 208     if mode2 = 1 then a2 <- ra-1
 209     if mode2 = 2 then a2 <- ra+1
 210     if mode2 = 3 then a2 <- ¬(ra+1)
 211     a1 <- a1 & mask
 212     a2 <- a2 & mask
 213     # select operator
 214     mode3 <- bm[0:1]
 215     if mode3 = 0 then result <- a1 | a2
 216     if mode3 = 1 then result <- a1 & a2
 217     if mode3 = 2 then result <- a1 ^ a2
 218     if mode3 = 3 then result <- undefined([0]*XLEN)
 219     result <- result & mask
 220     # optionally restore masked-out bits
 221     if L = 1 then
 222         result <- result | (RA & ¬mask)
 223     RT <- result
 224
 225 Special Registers Altered:
 226
 227     None
 228
 229 # Load Floating-Point Immediate
 230
 231 DX-Form
 232
 233 * fmvis FRS,D
 234
 235 Pseudo-code:
 236
 237     bf16 <- d0 || d1 || d2
 238     fp32 <- bf16 || [0]*16
 239     FRS  <- DOUBLE(fp32)
 240
 241 Special Registers Altered:
 242
 243     None
 244
 245 # Float Replace Lower-Half Single, Immediate
 246
 247 DX-Form
 248
 249 * fishmv FRS,D
 250
 251 Pseudo-code:
 252
 253     fp32 <- SINGLE((FRS))
 254     fp32[16:31] <- d0 || d1 || d2
 255     FRS <- DOUBLE(fp32)
 256
 257 Special Registers Altered:
 258
 259     None