openpower/isa/av.mdwn

   1 <!-- DRAFT Instructions for PowerISA Version 3.0 B Book 1 -->
   2 <!-- https://libre-soc.org/openpower/sv/bitmanip/ -->
   3 <!-- https://libre-soc.org/openpower/sv/av_opcodes/ -->
   4
   5 # DRAFT Minimum/Maximum (Rc=1)
   6
   7 MM-Form
   8
   9 * minmax. RT,RA,RB,MMM (Rc=1)
  10
  11 Pseudo-code:
  12
  13     a <- (RA|0)
  14     b <- (RB)
  15     if MMM[0] then  # word mode
  16         # shift left by XLEN/2 to make the dword comparison
  17         # do word comparison of the original inputs
  18         a <- a[XLEN/2:XLEN-1] || [0] * XLEN/2
  19         b <- b[XLEN/2:XLEN-1] || [0] * XLEN/2
  20     if MMM[1] then  # signed mode
  21         # invert sign bits to make the unsigned comparison
  22         # do signed comparison of the original inputs
  23         a[0] <- ¬a[0]
  24         b[0] <- ¬b[0]
  25     # if Rc = 1 then store the result of comparing a and b to CR0
  26     if Rc = 1 then
  27         if a <u b then
  28             CR0 <- 0b100 || XER[SO]
  29         if a = b then
  30             CR0 <- 0b001 || XER[SO]
  31         if a >u b then
  32             CR0 <- 0b010 || XER[SO]
  33     if MMM[2] then  # max mode
  34         # swap a and b to make the less than comparison do
  35         # greater than comparison of the original inputs
  36         t <- a
  37         a <- b
  38         b <- t
  39     # store the entire selected source (even in word mode)
  40     # if Rc = 1 then store the result of comparing a and b to CR0
  41     if a <u b then RT <- (RA|0)
  42     else RT <- (RB)
  43
  44 Special Registers Altered:
  45
  46     CR0                     (if Rc=1)
  47
  48 # DRAFT Minimum/Maximum
  49
  50 MM-Form
  51
  52 * minmax RT,RA,RB,MMM (Rc=0)
  53
  54 Pseudo-code:
  55
  56     a <- (RA|0)
  57     b <- (RB)
  58     if MMM[0] then  # word mode
  59         # shift left by XLEN/2 to make the dword comparison
  60         # do word comparison of the original inputs
  61         a <- a[XLEN/2:XLEN-1] || [0] * XLEN/2
  62         b <- b[XLEN/2:XLEN-1] || [0] * XLEN/2
  63     if MMM[1] then  # signed mode
  64         # invert sign bits to make the unsigned comparison
  65         # do signed comparison of the original inputs
  66         a[0] <- ¬a[0]
  67         b[0] <- ¬b[0]
  68     # if Rc = 1 then store the result of comparing a and b to CR0
  69     # if Rc = 1 then
  70     #     if a <u b then
  71     #         CR0 <- 0b100 || XER[SO]
  72     #     if a = b then
  73     #         CR0 <- 0b001 || XER[SO]
  74     #     if a >u b then
  75     #         CR0 <- 0b010 || XER[SO]
  76     if MMM[2] then  # max mode
  77         # swap a and b to make the less than comparison do
  78         # greater than comparison of the original inputs
  79         t <- a
  80         a <- b
  81         b <- t
  82     # store the entire selected source (even in word mode)
  83     # if Rc = 1 then store the result of comparing a and b to CR0
  84     if a <u b then RT <- (RA|0)
  85     else RT <- (RB)
  86
  87 Special Registers Altered:
  88
  89     None
  90
  91 # DRAFT Average Add
  92
  93 X-Form
  94
  95 * avgadd  RT,RA,RB (Rc=0)
  96 * avgadd. RT,RA,RB (Rc=1)
  97
  98 Pseudo-code:
  99
 100     a <- [0] * (XLEN+1)
 101     b <- [0] * (XLEN+1)
 102     a[1:XLEN] <- (RA)
 103     b[1:XLEN] <- (RB)
 104     r <- (a + b + 1)
 105     RT <- r[0:XLEN-1]
 106
 107 Special Registers Altered:
 108
 109     CR0                     (if Rc=1)
 110
 111 # DRAFT Absolute Signed Difference
 112
 113 X-Form
 114
 115 * absds  RT,RA,RB (Rc=0)
 116 * absds. RT,RA,RB (Rc=1)
 117
 118 Pseudo-code:
 119
 120     if (RA) < (RB) then RT <- ¬(RA) + (RB) + 1
 121     else                RT <- ¬(RB) + (RA) + 1
 122
 123 Special Registers Altered:
 124
 125     CR0                     (if Rc=1)
 126
 127 # DRAFT Absolute Unsigned Difference
 128
 129 X-Form
 130
 131 * absdu  RT,RA,RB (Rc=0)
 132 * absdu. RT,RA,RB (Rc=1)
 133
 134 Pseudo-code:
 135
 136     if (RA) <u (RB) then RT <- ¬(RA) + (RB) + 1
 137     else                RT <- ¬(RB) + (RA) + 1
 138
 139 Special Registers Altered:
 140
 141     CR0                     (if Rc=1)
 142
 143 # DRAFT Absolute Accumulate Unsigned Difference
 144
 145 X-Form
 146
 147 * absdacu  RT,RA,RB (Rc=0)
 148 * absdacu. RT,RA,RB (Rc=1)
 149
 150 Pseudo-code:
 151
 152     if (RA) <u (RB) then r <- ¬(RA) + (RB) + 1
 153     else                 r <- ¬(RB) + (RA) + 1
 154     RT <- (RT) + r
 155
 156 Special Registers Altered:
 157
 158     CR0                     (if Rc=1)
 159
 160 # DRAFT Absolute Accumulate Signed Difference
 161
 162 X-Form
 163
 164 * absdacs  RT,RA,RB (Rc=0)
 165 * absdacs. RT,RA,RB (Rc=1)
 166
 167 Pseudo-code:
 168
 169     if (RA) < (RB) then r <- ¬(RA) + (RB) + 1
 170     else                r <- ¬(RB) + (RA) + 1
 171     RT <- (RT) + r
 172
 173 Special Registers Altered:
 174
 175     CR0                     (if Rc=1)
 176
 177 # Carry Propagate
 178
 179 X-Form
 180
 181 * cprop RT,RA,RB (Rc=0)
 182 * cprop. RT,RA,RB (Rc=1)
 183
 184 Pseudo-code:
 185
 186     P <- (RA)
 187     G <- (RB)
 188     temp <- (P|G)+G
 189     RT <- temp^P
 190
 191 Special Registers Altered:
 192
 193     CR0                    (if Rc=1)
 194
 195 # DRAFT Bitmanip Masked
 196
 197 BM2-Form
 198
 199 * bmask  RT,RA,RB,bm,L
 200
 201 Pseudo-code:
 202
 203     if _RB = 0 then mask <- [1] * XLEN
 204     else mask <- (RB)
 205     ra <- (RA) & mask
 206     a1 <- ra
 207     if bm[4] = 0 then a1 <- ¬ra
 208     mode2 <- bm[2:3]
 209     if mode2 = 0 then a2 <- (¬ra)+1
 210     if mode2 = 1 then a2 <- ra-1
 211     if mode2 = 2 then a2 <- ra+1
 212     if mode2 = 3 then a2 <- ¬(ra+1)
 213     a1 <- a1 & mask
 214     a2 <- a2 & mask
 215     # select operator
 216     mode3 <- bm[0:1]
 217     if mode3 = 0 then result <- a1 | a2
 218     if mode3 = 1 then result <- a1 & a2
 219     if mode3 = 2 then result <- a1 ^ a2
 220     if mode3 = 3 then result <- undefined([0]*XLEN)
 221     result <- result & mask
 222     # optionally restore masked-out bits
 223     if L = 1 then
 224         result <- result | (RA & ¬mask)
 225     RT <- result
 226
 227 Special Registers Altered:
 228
 229     None
 230
 231 # Load Floating-Point Immediate
 232
 233 DX-Form
 234
 235 * fmvis FRS,D
 236
 237 Pseudo-code:
 238
 239     bf16 <- d0 || d1 || d2
 240     fp32 <- bf16 || [0]*16
 241     FRS  <- DOUBLE(fp32)
 242
 243 Special Registers Altered:
 244
 245     None
 246
 247 # Float Replace Lower-Half Single, Immediate
 248
 249 DX-Form
 250
 251 * fishmv FRS,D
 252
 253 Pseudo-code:
 254
 255     fp32 <- SINGLE((FRS))
 256     fp32[16:31] <- d0 || d1 || d2
 257     FRS <- DOUBLE(fp32)
 258
 259 Special Registers Altered:
 260
 261     None