1 <!-- DRAFT Instructions for PowerISA Version 3.0 B Book 1 -->
2 <!-- https://libre-soc.org/openpower/sv/bitmanip/ -->
3 <!-- https://libre-soc.org/openpower/sv/av_opcodes/ -->
5 # DRAFT Fixed Point Signed Max
10 * maxs. RT,RA,RB (Rc=1)
14 if (RA) > (RB) then RT <- (RA)
17 Special Registers Altered:
21 # DRAFT Fixed Point Unsigned Max
25 * maxu RT,RA,RB (Rc=0)
26 * maxu. RT,RA,RB (Rc=1)
30 if (RA) >u (RB) then RT <- (RA)
33 Special Registers Altered:
37 # DRAFT Fixed Point Signed Min
41 * mins RT,RA,RB (Rc=0)
42 * mins. RT,RA,RB (Rc=1)
46 if (RA) < (RB) then RT <- (RA)
49 Special Registers Altered:
53 # DRAFT Fixed Point Unsigned Min
57 * minu RT,RA,RB (Rc=0)
58 * minu. RT,RA,RB (Rc=1)
62 if (RA) <u (RB) then RT <- (RA)
65 Special Registers Altered:
73 * avgadd RT,RA,RB (Rc=0)
74 * avgadd. RT,RA,RB (Rc=1)
85 Special Registers Altered:
89 # DRAFT Absolute Signed Difference
93 * absds RT,RA,RB (Rc=0)
94 * absds. RT,RA,RB (Rc=1)
98 if (RA) < (RB) then RT <- ¬(RA) + (RB) + 1
99 else RT <- ¬(RB) + (RA) + 1
101 Special Registers Altered:
105 # DRAFT Absolute Unsigned Difference
109 * absdu RT,RA,RB (Rc=0)
110 * absdu. RT,RA,RB (Rc=1)
114 if (RA) <u (RB) then RT <- ¬(RA) + (RB) + 1
115 else RT <- ¬(RB) + (RA) + 1
117 Special Registers Altered:
121 # DRAFT Absolute Accumulate Unsigned Difference
125 * absdacu RT,RA,RB (Rc=0)
126 * absdacu. RT,RA,RB (Rc=1)
130 if (RA) <u (RB) then r <- ¬(RA) + (RB) + 1
131 else r <- ¬(RB) + (RA) + 1
134 Special Registers Altered:
138 # DRAFT Absolute Accumulate Signed Difference
142 * absdacs RT,RA,RB (Rc=0)
143 * absdacs. RT,RA,RB (Rc=1)
147 if (RA) < (RB) then r <- ¬(RA) + (RB) + 1
148 else r <- ¬(RB) + (RA) + 1
151 Special Registers Altered:
159 * cprop RT,RA,RB (Rc=0)
160 * cprop RT,RA,RB (Rc=1)
169 Special Registers Altered:
173 # DRAFT Bitmanip Masked
181 if _RB = 0 then mask <- [1] * XLEN
185 if bm[4] = 0 then a1 <- ¬ra
187 if mode2 = 0 then a2 <- (¬ra)+1
188 if mode2 = 1 then a2 <- ra-1
189 if mode2 = 2 then a2 <- ra+1
190 if mode2 = 3 then a2 <- ¬(ra+1)
195 if mode3 = 0 then result <- a1 | a2
196 if mode3 = 1 then result <- a1 & a2
197 if mode3 = 2 then result <- a1 ^ a2
198 if mode3 = 3 then result <- undefined([0]*XLEN)
199 result <- result & mask
200 # optionally restore masked-out bits
202 result <- result | (RA & ¬mask)
205 Special Registers Altered:
209 # Load Floating-Point Immediate
217 bf16 <- d0 || d1 || d2
218 fp32 <- bf16 || [0]*16
221 Special Registers Altered:
225 # Float Replace Lower-Half Single, Immediate
233 fp32 <- SINGLE((FRS))
234 fp32[16:31] <- d0 || d1 || d2
237 Special Registers Altered: