openpower/isa/av.mdwn

   1 <!-- DRAFT Instructions for PowerISA Version 3.0 B Book 1 -->
   2 <!-- https://libre-soc.org/openpower/sv/bitmanip/ -->
   3 <!-- https://libre-soc.org/openpower/sv/av_opcodes/ -->
   4
   5 # DRAFT Fixed Point Signed Max
   6
   7 X-Form
   8
   9 * maxs  RT,RA,RB (Rc=0)
  10 * maxs. RT,RA,RB (Rc=1)
  11
  12 Pseudo-code:
  13
  14     if   (RA) > (RB) then RT <- (RA)
  15     else                  RT <- (RB)
  16
  17 Special Registers Altered:
  18
  19     CR0                     (if Rc=1)
  20
  21 # DRAFT Fixed Point Unsigned Max
  22
  23 X-Form
  24
  25 * maxu  RT,RA,RB (Rc=0)
  26 * maxu. RT,RA,RB (Rc=1)
  27
  28 Pseudo-code:
  29
  30     if   (RA) >u (RB) then RT <- (RA)
  31     else                   RT <- (RB)
  32
  33 Special Registers Altered:
  34
  35     CR0                     (if Rc=1)
  36
  37 # DRAFT Fixed Point Signed Min
  38
  39 X-Form
  40
  41 * mins  RT,RA,RB (Rc=0)
  42 * mins. RT,RA,RB (Rc=1)
  43
  44 Pseudo-code:
  45
  46     if   (RA) < (RB) then RT <- (RA)
  47     else                  RT <- (RB)
  48
  49 Special Registers Altered:
  50
  51     CR0                     (if Rc=1)
  52
  53 # DRAFT Fixed Point Unsigned Min
  54
  55 X-Form
  56
  57 * minu  RT,RA,RB (Rc=0)
  58 * minu. RT,RA,RB (Rc=1)
  59
  60 Pseudo-code:
  61
  62     if   (RA) <u (RB) then RT <- (RA)
  63     else                   RT <- (RB)
  64
  65 Special Registers Altered:
  66
  67     CR0                     (if Rc=1)
  68
  69 # DRAFT Average Add
  70
  71 X-Form
  72
  73 * avgadd  RT,RA,RB (Rc=0)
  74 * avgadd. RT,RA,RB (Rc=1)
  75
  76 Pseudo-code:
  77
  78     a <- [0] * (XLEN+1)
  79     b <- [0] * (XLEN+1)
  80     a[1:XLEN] <- (RA)
  81     b[1:XLEN] <- (RB)
  82     r <- (a + b + 1)
  83     RT <- r[0:XLEN-1]
  84
  85 Special Registers Altered:
  86
  87     CR0                     (if Rc=1)
  88
  89 # DRAFT Absolute Signed Difference
  90
  91 X-Form
  92
  93 * absds  RT,RA,RB (Rc=0)
  94 * absds. RT,RA,RB (Rc=1)
  95
  96 Pseudo-code:
  97
  98     if (RA) < (RB) then RT <- ¬(RA) + (RB) + 1
  99     else                RT <- ¬(RB) + (RA) + 1
 100
 101 Special Registers Altered:
 102
 103     CR0                     (if Rc=1)
 104
 105 # DRAFT Absolute Unsigned Difference
 106
 107 X-Form
 108
 109 * absdu  RT,RA,RB (Rc=0)
 110 * absdu. RT,RA,RB (Rc=1)
 111
 112 Pseudo-code:
 113
 114     if (RA) <u (RB) then RT <- ¬(RA) + (RB) + 1
 115     else                RT <- ¬(RB) + (RA) + 1
 116
 117 Special Registers Altered:
 118
 119     CR0                     (if Rc=1)
 120
 121 # DRAFT Absolute Accumulate Unsigned Difference
 122
 123 X-Form
 124
 125 * absdacu  RT,RA,RB (Rc=0)
 126 * absdacu. RT,RA,RB (Rc=1)
 127
 128 Pseudo-code:
 129
 130     if (RA) <u (RB) then r <- ¬(RA) + (RB) + 1
 131     else                 r <- ¬(RB) + (RA) + 1
 132     RT <- (RT) + r
 133
 134 Special Registers Altered:
 135
 136     CR0                     (if Rc=1)
 137
 138 # DRAFT Absolute Accumulate Signed Difference
 139
 140 X-Form
 141
 142 * absdacs  RT,RA,RB (Rc=0)
 143 * absdacs. RT,RA,RB (Rc=1)
 144
 145 Pseudo-code:
 146
 147     if (RA) < (RB) then r <- ¬(RA) + (RB) + 1
 148     else                r <- ¬(RB) + (RA) + 1
 149     RT <- (RT) + r
 150
 151 Special Registers Altered:
 152
 153     CR0                     (if Rc=1)
 154
 155 # Carry Propagate
 156
 157 X-Form
 158
 159 * cprop RT,RA,RB (Rc=0)
 160 * cprop RT,RA,RB (Rc=1)
 161
 162 Pseudo-code:
 163
 164     P <- (RA)
 165     G <- (RB)
 166     temp <- (P|G)+G
 167     RT <- temp^P
 168
 169 Special Registers Altered:
 170
 171     CR0                    (if Rc=1)
 172
 173 # DRAFT Bitmanip Masked
 174
 175 BM2-Form
 176
 177 * bmask  RT,RA,RB,bm
 178
 179 Pseudo-code:
 180
 181     if _RB = 0 then mask <- [1] * XLEN
 182     else mask <- (RB)
 183     ra <- (RA) & mask
 184     a1 <- ra
 185     if bm[4] = 0 then a1 <- ¬ra
 186     mode2 <- bm[2:3]
 187     if mode2 = 0 then a2 <- (¬ra)+1
 188     if mode2 = 1 then a2 <- ra-1
 189     if mode2 = 2 then a2 <- ra+1
 190     if mode2 = 3 then a2 <- ¬(ra+1)
 191     a1 <- a1 & mask
 192     a2 <- a2 & mask
 193     # select operator
 194     mode3 <- bm[0:1]
 195     if mode3 = 0 then result <- a1 | a2
 196     if mode3 = 1 then result <- a1 & a2
 197     if mode3 = 2 then result <- a1 ^ a2
 198     if mode3 = 3 then result <- undefined([0]*XLEN)
 199     result <- result & mask
 200     # optionally restore masked-out bits
 201     if L = 1 then
 202         result <- result | (RA & ¬mask)
 203     RT <- result
 204
 205 Special Registers Altered:
 206
 207     None
 208
 209 # Load Floating-Point Immediate
 210
 211 DX-Form
 212
 213 * fmvis FRS,D
 214
 215 Pseudo-code:
 216
 217     bf16 <- d0 || d1 || d2
 218     fp32 <- bf16 || [0]*16
 219     FRS  <- DOUBLE(fp32)
 220
 221 Special Registers Altered:
 222
 223     None
 224
 225 # Float Replace Lower-Half Single, Immediate
 226
 227 DX-Form
 228
 229 * fishmv FRS,D
 230
 231 Pseudo-code:
 232
 233     fp32 <- SINGLE((FRS))
 234     fp32[16:31] <- d0 || d1 || d2
 235     FRS <- DOUBLE(fp32)
 236
 237 Special Registers Altered:
 238
 239     None