1 <!-- DRAFT Instructions for PowerISA Version 3.0 B Book 1 -->
2 <!-- https://libre-soc.org/openpower/sv/bitmanip/ -->
3 <!-- https://libre-soc.org/openpower/sv/av_opcodes/ -->
5 # DRAFT Fixed Point Signed Max (Rc=1)
9 * maxs. RT,RA,RB (Rc=1)
17 if a < b then c <- 0b100
18 else if a > b then c <- 0b010
22 Special Registers Altered:
26 # DRAFT Fixed Point Signed Max
30 * maxs RT,RA,RB (Rc=0)
34 if (RA) > (RB) then RT <- (RA)
37 Special Registers Altered:
41 # DRAFT Fixed Point Unsigned Max
45 * maxu RT,RA,RB (Rc=0)
46 * maxu. RT,RA,RB (Rc=1)
50 if (RA) >u (RB) then RT <- (RA)
53 Special Registers Altered:
57 # DRAFT Fixed Point Signed Min
61 * mins RT,RA,RB (Rc=0)
62 * mins. RT,RA,RB (Rc=1)
66 if (RA) < (RB) then RT <- (RA)
69 Special Registers Altered:
73 # DRAFT Fixed Point Unsigned Min
77 * minu RT,RA,RB (Rc=0)
78 * minu. RT,RA,RB (Rc=1)
82 if (RA) <u (RB) then RT <- (RA)
85 Special Registers Altered:
93 * avgadd RT,RA,RB (Rc=0)
94 * avgadd. RT,RA,RB (Rc=1)
105 Special Registers Altered:
109 # DRAFT Absolute Signed Difference
113 * absds RT,RA,RB (Rc=0)
114 * absds. RT,RA,RB (Rc=1)
118 if (RA) < (RB) then RT <- ¬(RA) + (RB) + 1
119 else RT <- ¬(RB) + (RA) + 1
121 Special Registers Altered:
125 # DRAFT Absolute Unsigned Difference
129 * absdu RT,RA,RB (Rc=0)
130 * absdu. RT,RA,RB (Rc=1)
134 if (RA) <u (RB) then RT <- ¬(RA) + (RB) + 1
135 else RT <- ¬(RB) + (RA) + 1
137 Special Registers Altered:
141 # DRAFT Absolute Accumulate Unsigned Difference
145 * absdacu RT,RA,RB (Rc=0)
146 * absdacu. RT,RA,RB (Rc=1)
150 if (RA) <u (RB) then r <- ¬(RA) + (RB) + 1
151 else r <- ¬(RB) + (RA) + 1
154 Special Registers Altered:
158 # DRAFT Absolute Accumulate Signed Difference
162 * absdacs RT,RA,RB (Rc=0)
163 * absdacs. RT,RA,RB (Rc=1)
167 if (RA) < (RB) then r <- ¬(RA) + (RB) + 1
168 else r <- ¬(RB) + (RA) + 1
171 Special Registers Altered:
179 * cprop RT,RA,RB (Rc=0)
180 * cprop. RT,RA,RB (Rc=1)
189 Special Registers Altered:
193 # DRAFT Bitmanip Masked
197 * bmask RT,RA,RB,bm,L
201 if _RB = 0 then mask <- [1] * XLEN
205 if bm[4] = 0 then a1 <- ¬ra
207 if mode2 = 0 then a2 <- (¬ra)+1
208 if mode2 = 1 then a2 <- ra-1
209 if mode2 = 2 then a2 <- ra+1
210 if mode2 = 3 then a2 <- ¬(ra+1)
215 if mode3 = 0 then result <- a1 | a2
216 if mode3 = 1 then result <- a1 & a2
217 if mode3 = 2 then result <- a1 ^ a2
218 if mode3 = 3 then result <- undefined([0]*XLEN)
219 result <- result & mask
220 # optionally restore masked-out bits
222 result <- result | (RA & ¬mask)
225 Special Registers Altered:
229 # Load Floating-Point Immediate
237 bf16 <- d0 || d1 || d2
238 fp32 <- bf16 || [0]*16
241 Special Registers Altered:
245 # Float Replace Lower-Half Single, Immediate
253 fp32 <- SINGLE((FRS))
254 fp32[16:31] <- d0 || d1 || d2
257 Special Registers Altered: