openpower/isa/branch.mdwn

   1 <!-- Instructions here described in PowerISA Version 3.0 B Book 1 -->
   2
   3 <!-- Section 2.4 Branch Instructions. Pages 33 - 39 -->
   4
   5 <!-- The sequence of instruction execution can be changed by the Branch -->
   6 <!-- instructions. Because all instructions are on word boundaries, bits 62 and 63 -->
   7 <!-- of the generated branch target address are ignored by the processor in -->
   8 <!-- performing the branch. -->
   9
  10 <!-- target_addr specifies the branch target address. -->
  11
  12 <!-- If AA=0 then the branch target address is the sum of LI || 0b00 sign-extended -->
  13 <!-- and the address of this instruction, with the high-order 32 bits of the branch -->
  14 <!-- target address set to 0 in 32-bit mode. -->
  15
  16 <!-- If AA=1 then the branch target address is the value LI || 0b00 sign-extended, -->
  17 <!-- with the high-order 32 bits of the branch target address set to 0 in 32-bit -->
  18 <!-- mode. -->
  19
  20 <!-- If LK=1 then the effective address of the instruction following the Branch -->
  21 <!-- instruction is placed into the Link Register. -->
  22
  23 # Branch
  24
  25 I-Form
  26
  27 * b target_addr (AA=0 LK=0)
  28 * ba target_addr (AA=1 LK=0)
  29 * bl target_addr (AA=0 LK=1)
  30 * bla target_addr (AA=1 LK=1)
  31
  32 Pseudo-code:
  33
  34     if AA then NIA  <-iea EXTS(LI || 0b00)
  35     else       NIA  <-iea CIA + EXTS(LI || 0b00)
  36     if LK then LR <-iea  CIA + 4
  37
  38 Special Registers Altered:
  39
  40     LR                       (if LK=1)
  41
  42 # Branch Conditional
  43
  44 B-Form
  45
  46 * bc BO,BI,target_addr (AA=0 LK=0)
  47 * bca BO,BI,target_addr (AA=1 LK=0)
  48 * bcl BO,BI,target_addr (AA=0 LK=1)
  49 * bcla BO,BI,target_addr (AA=1 LK=1)
  50
  51 Pseudo-code:
  52
  53     if (mode_is_64bit) then M <- 0
  54     else M <- 32
  55     if ¬BO[2] then CTR <- CTR - 1
  56     ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
  57     cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1])
  58     if ctr_ok & cond_ok then
  59       if AA then NIA <-iea EXTS(BD || 0b00)
  60       else       NIA <-iea CIA + EXTS(BD || 0b00)
  61     if LK then LR  <-iea  CIA + 4
  62
  63 Special Registers Altered:
  64
  65     CTR                    (if BO2=0)
  66     LR                       (if LK=1)
  67
  68 # Branch Conditional to Link Register
  69
  70 XL-Form
  71
  72 * bclr BO,BI,BH (LK=0)
  73 * bclrl BO,BI,BH (LK=1)
  74
  75 Pseudo-code:
  76
  77     if (mode_is_64bit) then M <- 0
  78     else M <- 32
  79     if ¬BO[2]  then CTR <- CTR - 1
  80     ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
  81     cond_ok <- BO[0] | ¬(CR[BI+32] ^  BO[1])
  82     if ctr_ok & cond_ok then NIA <-iea LR[0:61] || 0b00
  83     if LK then LR <-iea CIA + 4
  84
  85 Special Registers Altered:
  86
  87     CTR                    (if BO2=0)
  88     LR                       (if LK=1)
  89
  90 # Branch Conditional to Count Register
  91
  92 XL-Form
  93
  94 * bcctr BO,BI,BH (LK=0)
  95 * bcctrl BO,BI,BH (LK=1)
  96
  97 Pseudo-code:
  98
  99     cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1])
 100     if cond_ok then NIA <-iea CTR[0:61] || 0b00
 101     if LK then LR <-iea CIA + 4
 102
 103 Special Registers Altered:
 104
 105     LR                     (if LK=1)
 106
 107 # Branch Conditional to Branch Target Address Register
 108
 109 XL-Form
 110
 111 * bctar BO,BI,BH (LK=0)
 112 * bctarl BO,BI,BH (LK=1)
 113
 114 Pseudo-code:
 115
 116     if (mode_is_64bit) then M <- 0
 117     else M <- 32
 118     if ¬BO[2] then CTR <- CTR - 1
 119     ctr_ok <- BO[2]  | ((CTR[M:63] != 0) ^ BO[3])
 120     cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1])
 121     if ctr_ok & cond_ok then NIA <-iea TAR[0:61]  || 0b00
 122     if LK then LR <-iea  CIA + 4
 123
 124 Special Registers Altered:
 125
 126     CTR                    (if BO2=0)
 127     LR                       (if LK=1)
 128
 129
 130 <!-- Checked March 2021 -->