openpower/isa/butterfly.mdwn

   1 <!-- SVP64 Butterfly DCT Instructions here described are based on -->
   2
   3 <!-- PLEASE NOTE THESE ARE UNAPPROVED AND DRAFT, NOT SUBMITTED TO OPF ISA WG -->
   4
   5 # [DRAFT] Integer Butterfly Multiply Add/Sub FFT/DCT
   6
   7 A-Form
   8
   9 * maddsubrs  RT,RA,SH,RB
  10
  11 Pseudo-code:
  12
  13     n <- SH
  14     sum <- (RT) + (RA)
  15     diff <- (RT) - (RA)
  16     prod1 <- MULS(RB, sum)
  17     prod1_lo <- prod1[XLEN:(XLEN*2)-1]
  18     prod2 <- MULS(RB, diff)
  19     prod2_lo <- prod2[XLEN:(XLEN*2)-1]
  20     if n = 0 then
  21         RT <- prod1_lo
  22         RS <- prod2_lo
  23     else
  24         round <- [0]*XLEN
  25         round[XLEN -n] <- 1
  26         prod1_lo <- prod1_lo + round
  27         prod2_lo <- prod2_lo + round
  28         m <- MASK(n, (XLEN-1))
  29         res1 <- ROTL64(prod1_lo, XLEN-n) & m
  30         res2 <- ROTL64(prod2_lo, XLEN-n) & m
  31         signbit1 <- prod1_lo[0]
  32         signbit2 <- prod2_lo[0]
  33         smask1 <- ([signbit1]*XLEN) & ¬m
  34         smask2 <- ([signbit2]*XLEN) & ¬m
  35         RT <- (res1 | smask1)
  36         RS <- (res2 | smask2)
  37
  38 Special Registers Altered:
  39
  40     None
  41
  42 # [DRAFT] Integer Butterfly Multiply Add and Accumulate FFT/DCT
  43
  44 A-Form
  45
  46 * maddrs  RT,RA,SH,RB
  47
  48 Pseudo-code:
  49
  50     n <- SH
  51     prod <- MULS(RB, RA)
  52     prod_lo <- prod[XLEN:(XLEN*2)-1]
  53     if n = 0 then
  54         RT <- (RT) + prod_lo
  55         RS <- (RS) - prod_lo
  56     else
  57         res1 <- (RT) + prod_lo
  58         res2 <- (RS) - prod_lo
  59         round <- [0]*XLEN
  60         round[XLEN -n] <- 1
  61         res1 <- res1 + round
  62         res2 <- res2 + round
  63         signbit1 <- res1[0]
  64         signbit2 <- res2[0]
  65         m <- MASK(n, (XLEN-1))
  66         res1 <- ROTL64(res1, XLEN-n) & m
  67         res2 <- ROTL64(res2, XLEN-n) & m
  68         smask1 <- ([signbit1]*XLEN) & ¬m
  69         smask2 <- ([signbit2]*XLEN) & ¬m
  70         RT <- (res1 | smask1)
  71         RS <- (res2 | smask2)
  72
  73 Special Registers Altered:
  74
  75     None