pysvp64db: fix traversal
[openpower-isa.git] / openpower / isa / condition.mdwn
1 <!-- Instructions here described in PowerISA Version 3.0 B Book 1 -->
2
3 <!-- Section 2.5.1 Condition Register Logical Instructions Pages 40 - 41 -->
4
5 <!-- The Condition Register Logical instructions have preferred forms; see Section -->
6 <!-- 1.9.1. -->
7
8 <!-- In the preferred forms, the BT and BB fields satisfy the following rule: -->
9
10 <!-- * The bit specified by BT is in the same Condition Register field as the bit -->
11 <!-- specified by BB. -->
12
13 # Condition Register AND
14
15 XL-Form
16
17 * crand BT,BA,BB
18
19 Pseudo-code:
20
21 CR[BT+32] <- CR[BA+32] & CR[BB+32]
22
23 Special Registers Altered:
24
25 CR[BT+32]
26
27 # Condition Register NAND
28
29 XL-Form
30
31 * crnand BT,BA,BB
32
33 Pseudo-code:
34
35 CR[BT+32] <- ¬(CR[BA+32] & CR[BB+32])
36
37 Special Registers Altered:
38
39 CR[BT+32]
40
41 # Condition Register OR
42
43 XL-Form
44
45 * cror BT,BA,BB
46
47 Pseudo-code:
48
49 CR[BT+32] <- CR[BA+32] | CR[BB+32]
50
51 Special Registers Altered:
52
53 CR[BT+32]
54
55 # Condition Register XOR
56
57 XL-Form
58
59 * crxor BT,BA,BB
60
61 Pseudo-code:
62
63 CR[BT+32] <- CR[BA+32] ^ CR[BB+32]
64
65 Special Registers Altered:
66
67 CR[BT+32]
68
69 # Condition Register NOR
70
71 XL-Form
72
73 * crnor BT,BA,BB
74
75 Pseudo-code:
76
77 CR[BT+32] <- ¬(CR[BA+32] | CR[BB+32])
78
79 Special Registers Altered:
80
81 CR[BT+32]
82
83 # Condition Register Equivalent
84
85 XL-Form
86
87 * creqv BT,BA,BB
88
89 Pseudo-code:
90
91 CR[BT+32] <- ¬(CR[BA+32] ^ CR[BB+32])
92
93 Special Registers Altered:
94
95 CR[BT+32]
96
97 # Condition Register AND with Complement
98
99 XL-Form
100
101 * crandc BT,BA,BB
102
103 Pseudo-code:
104
105 CR[BT+32] <- CR[BA+32] & ¬CR[BB+32]
106
107 Special Registers Altered:
108
109 CR[BT+32]
110
111 # Condition Register OR with Complement
112
113 XL-Form
114
115 * crorc BT,BA,BB
116
117 Pseudo-code:
118
119 CR[BT+32] <- CR[BA+32] | ¬CR[BB+32]
120
121 Special Registers Altered:
122
123 CR[BT+32]
124
125 # Move Condition Register Field
126
127 XL-Form
128
129 * mcrf BF,BFA
130
131 Pseudo-code:
132
133 CR[4*BF+32:4*BF+35] <- CR[4*BFA+32:4*BFA+35]
134
135 Special Registers Altered:
136
137 CR field BF
138
139 <!-- Checked March 2021 -->