1 <!-- Instructions here described in PowerISA Version 3.0 B Book 1 -->
3 <!-- Section 2.5.1 Condition Register Logical Instructions Pages 40 - 41 -->
5 <!-- The Condition Register Logical instructions have preferred forms; see Section -->
8 <!-- In the preferred forms, the BT and BB fields satisfy the following rule: -->
10 <!-- * The bit specified by BT is in the same Condition Register field as the bit -->
11 <!-- specified by BB. -->
13 # Condition Register AND
21 CR[BT+32] <- CR[BA+32] & CR[BB+32]
23 Special Registers Altered:
27 # Condition Register NAND
35 CR[BT+32] <- ¬(CR[BA+32] & CR[BB+32])
37 Special Registers Altered:
41 # Condition Register OR
49 CR[BT+32] <- CR[BA+32] | CR[BB+32]
51 Special Registers Altered:
55 # Condition Register XOR
63 CR[BT+32] <- CR[BA+32] ^ CR[BB+32]
65 Special Registers Altered:
69 # Condition Register NOR
77 CR[BT+32] <- ¬(CR[BA+32] | CR[BB+32])
79 Special Registers Altered:
83 # Condition Register Equivalent
91 CR[BT+32] <- ¬(CR[BA+32] ^ CR[BB+32])
93 Special Registers Altered:
97 # Condition Register AND with Complement
105 CR[BT+32] <- CR[BA+32] & ¬CR[BB+32]
107 Special Registers Altered:
111 # Condition Register OR with Complement
119 CR[BT+32] <- CR[BA+32] | ¬CR[BB+32]
121 Special Registers Altered:
125 # Move Condition Register Field
133 CR[4*BF+32:4*BF+35] <- CR[4*BFA+32:4*BFA+35]
135 Special Registers Altered:
139 <!-- Checked March 2021 -->