openpower/isa/fixedldstcache.mdwn

   1 <!-- Instructions here described in PowerISA Version 3.0 B Book 1 -->
   2
   3 <!-- Section 4.4.1 Fixed-Point Load and Store Caching Inhibited Instructions. Pages 965 - 967 -->
   4
   5 <!-- The storage accesses caused by the instructions described in this section are -->
   6 <!-- performed as though the specified storage location is Caching Inhibited and -->
   7 <!-- Guarded. The instructions can be executed only in hypervisor state. Software -->
   8 <!-- must ensure that the specified storage location is not in the caches. If the -->
   9 <!-- specified storage location is in a cache, the results are undefined. -->
  10
  11
  12 # Load Byte and Zero Caching Inhibited Indexed
  13
  14 X-Form
  15
  16 * lbzcix RT,RA,RB
  17
  18 Pseudo-code:
  19
  20     b <- (RA|0)
  21     EA <- b + (RB)
  22     RT <- [0] * 56 || MEM(EA, 1)
  23
  24 Special Registers Altered:
  25
  26     None
  27
  28 # Load Halfword and Zero Caching Inhibited Indexed
  29
  30 X-Form
  31
  32 * lhzcix RT,RA,RB
  33
  34 Pseudo-code:
  35
  36     b <- (RA|0)
  37     EA <- b + (RB)
  38     RT <- [0] * 48 || MEM(EA, 2)
  39
  40 Special Registers Altered:
  41
  42     None
  43
  44 # Load Word and Zero Caching Inhibited Indexed
  45
  46 X-Form
  47
  48 * lwzcix RT,RA,RB
  49
  50 Pseudo-code:
  51
  52     b <- (RA|0)
  53     EA <- b + (RB)
  54     RT <- [0] * 32 || MEM(EA, 4)
  55
  56 Special Registers Altered:
  57
  58     None
  59
  60 # Load Doubleword Caching Inhibited Indexed
  61
  62 X-Form
  63
  64 * ldcix RT,RA,RB
  65
  66 Pseudo-code:
  67
  68     b <- (RA|0)
  69     EA <- b + (RB)
  70     RT <- MEM(EA, 8)
  71
  72 Special Registers Altered:
  73
  74     None
  75
  76 # Store Byte Caching Inhibited Indexed
  77
  78 X-Form
  79
  80 * stbcix RS,RA,RB
  81
  82 Pseudo-code:
  83
  84     b <- (RA|0)
  85     EA <- b + (RB)
  86     MEM(EA, 1) <- (RS)[56:63]
  87
  88 Special Registers Altered:
  89
  90     None
  91
  92 # Store Halfword Caching Inhibited Indexed
  93
  94 X-Form
  95
  96 * sthcix RS,RA,RB
  97
  98 Pseudo-code:
  99
 100     b <- (RA|0)
 101     EA <- b + (RB)
 102     MEM(EA, 2) <- (RS)[48:63]
 103
 104 Special Registers Altered:
 105
 106     None
 107
 108 # Store Word Caching Inhibited Indexed
 109
 110 X-Form
 111
 112 * stwcix RS,RA,RB
 113
 114 Pseudo-code:
 115
 116     b <- (RA|0)
 117     EA <- b + (RB)
 118     MEM(EA, 4) <- (RS)[32:63]
 119
 120 Special Registers Altered:
 121
 122     None
 123
 124 # Store Doubleword Caching Inhibited Indexed
 125
 126 X-Form
 127
 128 * stdcix RS,RA,RB
 129
 130 Pseudo-code:
 131
 132     b <- (RA|0)
 133     EA <- b + (RB)
 134     MEM(EA, 8) <- (RS)
 135
 136 Special Registers Altered:
 137
 138     None
 139
 140 <!-- Checked March 2021 -->