openpower/isa/fixedload.mdwn

   1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
   2
   3 <!-- This defines instructions that load from RAM to a register -->
   4
   5 <!-- Note that these pages also define equivalent store instructions, -->
   6 <!-- these are described in fixedstore.mdwn -->
   7
   8 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
   9 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
  10 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
  11 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
  12 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
  13 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
  14 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
  15
  16
  17
  18 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
  19
  20 <!-- The byte, halfword, word, or doubleword in storage addressed by EA is loaded -->
  21 <!-- into register RT. -->
  22
  23 <!-- Many of the Load instructions have an “update” form, in which register RA is -->
  24 <!-- updated with the effective address. For these forms, if RA!=0 and RA!=RT, the -->
  25 <!-- effective address is placed into register RA and the storage element (byte, -->
  26 <!-- halfword, word, or doubleword) addressed by EA is loaded into RT. -->
  27
  28
  29 # Load Byte and Zero
  30
  31 D-Form
  32
  33 * lbz RT,D(RA)
  34
  35 Pseudo-code:
  36
  37     b <- (RA|0)
  38     EA <- b + EXTS(D)
  39     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  40
  41 Description:
  42
  43     Let the effective address (EA) be the sum (RA|0)+ D.
  44     The byte in storage addressed by EA is loaded into
  45     RT[56:63]. RT[0:55] are set to 0.
  46
  47 Special Registers Altered:
  48
  49     None
  50
  51 # Load Byte and Zero Indexed
  52
  53 X-Form
  54
  55 * lbzx RT,RA,RB
  56
  57 Pseudo-code:
  58
  59     b <- (RA|0)
  60     EA <- b + (RB)
  61     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  62
  63 Description:
  64
  65     Let the effective address (EA) be the sum
  66     (RA|0)+ (RB). The byte in storage addressed by EA is
  67     loaded into RT[56:63] . RT[0:55] are set to 0.
  68
  69 Special Registers Altered:
  70
  71     None
  72
  73 # Load Byte and Zero with Update
  74
  75 D-Form
  76
  77 * lbzu RT,D(RA)
  78
  79 Pseudo-code:
  80
  81     EA <- (RA) + EXTS(D)
  82     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  83     RA <- EA
  84
  85 Description:
  86
  87     Let the effective address (EA) be the sum (RA)+ D. The
  88     byte in storage addressed by EA is loaded into RT[56:63].
  89     RT[0:55] are set to 0.
  90
  91     EA is placed into register RA.
  92
  93     If RA=0 or RA=RT, the instruction form is invalid.
  94
  95 Special Registers Altered:
  96
  97     None
  98
  99 # Load Byte and Zero with Update Indexed
 100
 101 X-Form
 102
 103 * lbzux RT,RA,RB
 104
 105 Pseudo-code:
 106
 107     EA <- (RA) + (RB)
 108     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
 109     RA <- EA
 110
 111 Description:
 112
 113     Let the effective address (EA) be the sum (RA)+ (RB).
 114     The byte in storage addressed by EA is loaded into
 115     RT[56:63]. RT[0:55] are set to 0.
 116
 117     EA is placed into register RA.
 118
 119     If RA=0 or RA=RT, the instruction form is invalid.
 120
 121 Special Registers Altered:
 122
 123     None
 124
 125 # Load Halfword and Zero
 126
 127 D-Form
 128
 129 * lhz RT,D(RA)
 130
 131 Pseudo-code:
 132
 133     b <- (RA|0)
 134     EA <- b + EXTS(D)
 135     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 136
 137 Description:
 138
 139     Let the effective address (EA) be the sum (RA|0)+ D.
 140     The halfword in storage addressed by EA is loaded into
 141     RT[48:63]. RT[0:47] are set to 0.
 142
 143 Special Registers Altered:
 144
 145     None
 146
 147 # Load Halfword and Zero Indexed
 148
 149 X-Form
 150
 151 * lhzx RT,RA,RB
 152
 153 Pseudo-code:
 154
 155     b <- (RA|0)
 156     EA <- b + (RB)
 157     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 158
 159 Description:
 160
 161     Let the effective address (EA) be the sum
 162     (RA|0)+ (RB). The halfword in storage addressed by
 163     EA is loaded into RT[48:63]. RT[0:47] are set to 0.
 164
 165 Special Registers Altered:
 166
 167     None
 168
 169 # Load Halfword and Zero with Update
 170
 171 D-Form
 172
 173 * lhzu RT,D(RA)
 174
 175 Pseudo-code:
 176
 177     EA <- (RA) + EXTS(D)
 178     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 179     RA <- EA
 180
 181 Description:
 182
 183     Let the effective address (EA) be the sum (RA)+ D. The
 184     halfword in storage addressed by EA is loaded into
 185     RT[48:63]. RT[0:47] are set to 0.
 186
 187     EA is placed into register RA.
 188
 189     If RA=0 or RA=RT, the instruction form is invalid.
 190
 191 Special Registers Altered:
 192
 193     None
 194
 195 # Load Halfword and Zero with Update Indexed
 196
 197 X-Form
 198
 199 * lhzux RT,RA,RB
 200
 201 Pseudo-code:
 202
 203     EA <- (RA) + (RB)
 204     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 205     RA <- EA
 206
 207 Description:
 208
 209     Let the effective address (EA) be the sum (RA)+ (RB).
 210     The halfword in storage addressed by EA is loaded into
 211     RT[48:63]. RT[0:47] are set to 0.
 212
 213     EA is placed into register RA.
 214
 215     If RA=0 or RA=RT, the instruction form is invalid.
 216
 217 Special Registers Altered:
 218
 219     None
 220
 221 # Load Halfword Algebraic
 222
 223 D-Form
 224
 225 * lha RT,D(RA)
 226
 227 Pseudo-code:
 228
 229     b <- (RA|0)
 230     EA <- b + EXTS(D)
 231     RT <- EXTS(MEM(EA, 2))
 232
 233 Description:
 234
 235     Let the effective address (EA) be the sum (RA|0)+ D.
 236     The halfword in storage addressed by EA is loaded into
 237     RT[48:63]. RT[0:47] are filled with a copy of bit 0 of the
 238     loaded halfword.
 239
 240 Special Registers Altered:
 241
 242     None
 243
 244 # Load Halfword Algebraic Indexed
 245
 246 X-Form
 247
 248 * lhax RT,RA,RB
 249
 250 Pseudo-code:
 251
 252     b <- (RA|0)
 253     EA <- b + (RB)
 254     RT <- EXTS(MEM(EA, 2))
 255
 256 Description:
 257
 258     Let the effective address (EA) be the sum
 259     (RA|0)+ (RB). The halfword in storage addressed by
 260     EA is loaded into RT[48:63] . RT[0:47] are filled with a copy
 261     of bit 0 of the loaded halfword.
 262
 263 Special Registers Altered:
 264
 265     None
 266
 267 # Load Halfword Algebraic with Update
 268
 269 D-Form
 270
 271 * lhau RT,D(RA)
 272
 273 Pseudo-code:
 274
 275     EA <- (RA) + EXTS(D)
 276     RT <- EXTS(MEM(EA, 2))
 277     RA <- EA
 278
 279 Description:
 280
 281     Let the effective address (EA) be the sum (RA)+ D. The
 282     halfword in storage addressed by EA is loaded into
 283     RT[48:63]. RT[0:47] are filled with a copy of bit 0 of the
 284     loaded halfword.
 285
 286     EA is placed into register RA.
 287
 288     If RA=0 or RA=RT, the instruction form is invalid.
 289
 290 Special Registers Altered:
 291
 292     None
 293
 294 # Load Halfword Algebraic with Update Indexed
 295
 296 X-Form
 297
 298 * lhaux RT,RA,RB
 299
 300 Pseudo-code:
 301
 302     EA <- (RA) + (RB)
 303     RT <- EXTS(MEM(EA, 2))
 304     RA <- EA
 305
 306 Description:
 307
 308     Let the effective address (EA) be the sum (RA)+ (RB).
 309     The halfword in storage addressed by EA is loaded into
 310     RT[48:63]. RT[0:47] are filled with a copy of bit 0 of the
 311     loaded halfword.
 312
 313     EA is placed into register RA.
 314
 315     If RA=0 or RA=RT, the instruction form is invalid.
 316
 317 Special Registers Altered:
 318
 319     None
 320
 321 # Load Word and Zero
 322
 323 D-Form
 324
 325 * lwz RT,D(RA)
 326
 327 Pseudo-code:
 328
 329     b <- (RA|0)
 330     EA <- b + EXTS(D)
 331     RT <- [0] * 32 || MEM(EA, 4)
 332
 333 Description:
 334
 335     Let the effective address (EA) be the sum (RA|0)+ D.
 336     The word in storage addressed by EA is loaded into
 337     RT[32:63]. RT[0:31] are set to 0.
 338
 339 Special Registers Altered:
 340
 341     None
 342
 343 # Load Word and Zero Indexed
 344
 345 X-Form
 346
 347 * lwzx RT,RA,RB
 348
 349 Pseudo-code:
 350
 351     b <- (RA|0)
 352     EA <- b + (RB)
 353     RT <- [0] * 32 || MEM(EA, 4)
 354
 355 Description:
 356
 357     Let the effective address (EA) be the sum
 358     (RA|0)+ (RB). The word in storage addressed by EA is
 359     loaded into RT[32:63] . RT[0:31] are set to 0.
 360
 361 Special Registers Altered:
 362
 363     None
 364
 365 # Load Word and Zero with Update
 366
 367 D-Form
 368
 369 * lwzu RT,D(RA)
 370
 371 Pseudo-code:
 372
 373     EA <- (RA) + EXTS(D)
 374     RT <- [0]*32 || MEM(EA, 4)
 375     RA <- EA
 376
 377 Description:
 378
 379     Let the effective address (EA) be the sum (RA)+ D. The
 380     word in storage addressed by EA is loaded into
 381     RT[32:63]. RT[0:31] are set to 0.
 382
 383     EA is placed into register RA.
 384
 385     If RA=0 or RA=RT, the instruction form is invalid.
 386
 387 Special Registers Altered:
 388
 389     None
 390
 391 # Load Word and Zero with Update Indexed
 392
 393 X-Form
 394
 395 * lwzux RT,RA,RB
 396
 397 Pseudo-code:
 398
 399     EA <- (RA) + (RB)
 400     RT <- [0] * 32 || MEM(EA, 4)
 401     RA <- EA
 402
 403 Description:
 404
 405     Let the effective address (EA) be the sum (RA)+ (RB).
 406     The word in storage addressed by EA is loaded into
 407     RT[32:63]. RT[0:31] are set to 0.
 408
 409     EA is placed into register RA.
 410
 411     If RA=0 or RA=RT, the instruction form is invalid.
 412
 413 Special Registers Altered:
 414
 415     None
 416
 417 # Load Word Algebraic
 418
 419 DS-Form
 420
 421 * lwa RT,DS(RA)
 422
 423 Pseudo-code:
 424
 425     b <- (RA|0)
 426     EA <- b + EXTS(DS || 0b00)
 427     RT <- EXTS(MEM(EA, 4))
 428
 429 Description:
 430
 431     Let the effective address (EA) be the sum
 432     (RA|0)+ (DS||0b00). The word in storage addressed by
 433     EA is loaded into RT[32:63] . RT[0:31] are filled with a copy
 434     of bit 0 of the loaded word.
 435
 436 Special Registers Altered:
 437
 438     None
 439
 440 # Load Word Algebraic Indexed
 441
 442 X-Form
 443
 444 * lwax RT,RA,RB
 445
 446 Pseudo-code:
 447
 448     b <- (RA|0)
 449     EA <- b + (RB)
 450     RT <- EXTS(MEM(EA, 4))
 451
 452 Description:
 453
 454     Let the effective address (EA) be the sum
 455     (RA|0)+ (RB). The word in storage addressed by EA is
 456     loaded into RT[32:63] . RT[0:31] are filled with a copy of bit 0
 457     of the loaded word.
 458
 459 Special Registers Altered:
 460
 461     None
 462
 463 # Load Word Algebraic with Update Indexed
 464
 465 X-Form
 466
 467 * lwaux RT,RA,RB
 468
 469 Pseudo-code:
 470
 471     EA <- (RA) + (RB)
 472     RT <- EXTS(MEM(EA, 4))
 473     RA <- EA
 474
 475 Description:
 476
 477     Let the effective address (EA) be the sum (RA)+ (RB).
 478     The word in storage addressed by EA is loaded into
 479     RT[32:63]. RT[0:31] are filled with a copy of bit 0 of the
 480     loaded word.
 481
 482     EA is placed into register RA.
 483
 484     If RA=0 or RA=RT, the instruction form is invalid.
 485
 486 Special Registers Altered:
 487
 488     None
 489
 490 # Load Doubleword
 491
 492 DS-Form
 493
 494 * ld RT,DS(RA)
 495
 496 Pseudo-code:
 497
 498     b <- (RA|0)
 499     EA <- b + EXTS(DS || 0b00)
 500     RT <- MEM(EA, 8)
 501
 502 Description:
 503
 504     Let the effective address (EA) be the sum
 505     (RA|0)+ (DS||0b00). The doubleword in storage
 506     addressed by EA is loaded into RT.
 507
 508 Special Registers Altered:
 509
 510     None
 511
 512 # Load Doubleword Indexed
 513
 514 X-Form
 515
 516 * ldx RT,RA,RB
 517
 518 Pseudo-code:
 519
 520     b <- (RA|0)
 521     EA <- b + (RB)
 522     RT <- MEM(EA, 8)
 523
 524 Description:
 525
 526     Let the effective address (EA) be the sum
 527     (RA|0)+ (RB). The doubleword in storage addressed by
 528     EA is loaded into RT.
 529
 530 Special Registers Altered:
 531
 532     None
 533
 534 # Load Doubleword with Update Indexed
 535
 536 DS-Form
 537
 538 * ldu RT,DS(RA)
 539
 540 Pseudo-code:
 541
 542     EA <- (RA) + EXTS(DS || 0b00)
 543     RT <- MEM(EA, 8)
 544     RA <- EA
 545
 546 Description:
 547
 548     Let the effective address (EA) be the sum
 549     (RA)+ (DS||0b00). The doubleword in storage
 550     addressed by EA is loaded into RT.
 551
 552     EA is placed into register RA.
 553
 554     If RA=0 or RA=RT, the instruction form is invalid.
 555
 556 Special Registers Altered:
 557
 558     None
 559
 560 # Load Doubleword with Update Indexed
 561
 562 X-Form
 563
 564 * ldux RT,RA,RB
 565
 566 Pseudo-code:
 567
 568     EA <- (RA) + (RB)
 569     RT <- MEM(EA, 8)
 570     RA <- EA
 571
 572 Description:
 573
 574     Let the effective address (EA) be the sum (RA)+ (RB).
 575     The doubleword in storage addressed by EA is loaded
 576     into RT.
 577
 578     EA is placed into register RA.
 579
 580     If RA=0 or RA=RT, the instruction form is invalid.
 581
 582 Special Registers Altered:
 583
 584     None
 585
 586 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
 587
 588 <!-- The contents of register RS are stored into the byte, halfword, word, or -->
 589 <!-- doubleword in storage addressed by EA. -->
 590
 591 <!-- Many of the Store instructions have an “update” form, in which register RA is -->
 592 <!-- updated with the effective address. For these forms, the following rules apply. -->
 593
 594 <!-- If RA!=0, the effective address is placed into register RA. -->
 595
 596 <!-- If RS=RA, the contents of register RS are copied to the target storage element -->
 597 <!-- and then EA is placed into RA (RS). -->
 598
 599 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
 600
 601 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
 602
 603 <!-- For lq, the quadword in storage addressed by EA is loaded into an even-odd pair -->
 604 <!-- of GPRs as follows. In Big-Endian mode, the even-numbered GPR is loaded with -->
 605 <!-- the doubleword from storage addressed by EA and the odd-numbered GPR is loaded -->
 606 <!-- with the doubleword addressed by EA+8. In Little-Endian mode, the even-numbered -->
 607 <!-- GPR is loaded with the byte-reversed doubleword from storage addressed by EA+8 -->
 608 <!-- and the odd-numbered GPR is loaded with the byte-reversed doubleword addressed -->
 609 <!-- by EA. -->
 610
 611 # Load Quadword
 612
 613 DQ-Form
 614
 615 * lq RTp,DQ(RA)
 616
 617 Pseudo-code:
 618
 619     b <- (RA|0)
 620     EA <- b + EXTS(DQ || 0b0000)
 621     RTp <- MEM(EA, 16)
 622
 623 Description
 624
 625     Let the effective address (EA) be the sum (RA|0)+
 626     (DQ||0b0000). The quadword in storage addressed by
 627     EA is loaded into register pair RTp.
 628
 629     If RTp is odd or RTp=RA, the instruction form is invalid.
 630     If RTp=RA, an attempt to execute this instruction will
 631     invoke the system illegal instruction error handler. (The
 632     RTp=RA case includes the case of RTp=RA=0.)
 633
 634     The quadword in storage addressed by EA is loaded
 635     into an even-odd pair of GPRs as follows. In
 636     Big-Endian mode, the even-numbered GPR is loaded
 637     with the doubleword from storage addressed by EA
 638     and the odd-numbered GPR is loaded with the double-
 639     word addressed by EA+8. In Little-Endian mode, the
 640     even-numbered GPR is loaded with the byte-reversed
 641     doubleword from storage addressed by EA+8 and the
 642     odd-numbered GPR is loaded with the byte-reversed
 643     doubleword addressed by EA.
 644
 645 Special Registers Altered:
 646
 647     None
 648
 649 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
 650
 651 # Load Halfword Byte-Reverse Indexed
 652
 653 X-Form
 654
 655 * lhbrx RT,RA,RB
 656
 657 Pseudo-code:
 658
 659     b <- (RA|0)
 660     EA <- b + (RB)
 661     load_data <- MEM(EA, 2)
 662     RT <- [0]*48 || load_data[8:15] || load_data[0:7]
 663
 664 Description:
 665
 666     Let the effective address (EA) be the sum (RA|0)+(RB).
 667     Bits 0:7 of the halfword in storage addressed by EA are
 668     loaded into RT 56:63 . Bits 8:15 of the halfword in storage
 669     addressed by EA are loaded into RT[48:55] . RT[0:47] are
 670     set to 0.
 671
 672 Special Registers Altered:
 673
 674     None
 675
 676 # Load Word Byte-Reverse Indexed
 677
 678 X-Form
 679
 680 * lwbrx RT,RA,RB
 681
 682 Pseudo-code:
 683
 684     b <- (RA|0)
 685     EA <- b + (RB)
 686     load_data <- MEM(EA, 4)
 687     RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
 688                     || load_data[8:15]  || load_data[0:7])
 689
 690 Description:
 691
 692     Let the effective address (EA) be the sum
 693     (RA|0)+ (RB). Bits 0:7 of the word in storage addressed
 694     by EA are loaded into RT[56:63]. Bits 8:15 of the word in
 695     storage addressed by EA are loaded into RT[48:55] . Bits
 696     16:23 of the word in storage addressed by EA are
 697     loaded into RT[40:47]. Bits 24:31 of the word in storage
 698     addressed by EA are loaded into RT 32:39 . RT[0:31] are
 699     set to 0.
 700
 701 Special Registers Altered:
 702
 703     None
 704
 705
 706 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
 707
 708 # Load Doubleword Byte-Reverse Indexed
 709
 710 X-Form
 711
 712 * ldbrx RT,RA,RB
 713
 714 Pseudo-code:
 715
 716     b <- (RA|0)
 717     EA <- b + (RB)
 718     load_data <- MEM(EA, 8)
 719     RT <- (load_data[56:63] || load_data[48:55]
 720         || load_data[40:47] || load_data[32:39]
 721         || load_data[24:31] || load_data[16:23]
 722         || load_data[8:15]  || load_data[0:7])
 723
 724 Description:
 725
 726     Let the effective address (EA) be the sum (RA|0)+(RB).
 727     Bits 0:7 of the doubleword in storage addressed by EA
 728     are loaded into RT[56:63] . Bits 8:15 of the doubleword in
 729     storage addressed by EA are loaded into RT[48:55] . Bits
 730     16:23 of the doubleword in storage addressed by EA
 731     are loaded into RT[40:47]. Bits 24:31 of the doubleword in
 732     storage addressed by EA are loaded into RT 32:39 . Bits
 733     32:39 of the doubleword in storage addressed by EA
 734     are loaded into RT[24:31]. Bits 40:47 of the doubleword in
 735     storage addressed by EA are loaded into RT[16:23] . Bits
 736     48:55 of the doubleword in storage addressed by EA
 737     are loaded into RT[8:15] . Bits 56:63 of the doubleword in
 738     storage addressed by EA are loaded into RT[0:7] .
 739
 740 Special Registers Altered:
 741
 742     None
 743
 744 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
 745
 746 # Load Multiple Word
 747
 748 D-Form
 749
 750 * lmw RT,D(RA)
 751
 752 Pseudo-code:
 753
 754     b <- (RA|0)
 755     EA <- b + EXTS(D)
 756     r <- RT[0:63]
 757     do while r <=  31
 758         GPR(r) <- [0]*32 || MEM(EA, 4)
 759         r <- r + 1
 760         EA <- EA + 4
 761
 762 Description:
 763
 764     Let n = (32-RT). Let the effective address (EA) be the
 765     sum (RA|0)+ D.
 766
 767     n consecutive words starting at EA are loaded into the
 768     low-order 32 bits of GPRs RT through 31. The
 769     high-order 32 bits of these GPRs are set to zero.
 770
 771     If RA is in the range of registers to be loaded, including
 772     the case in which RA=0, the instruction form is invalid.
 773
 774     This instruction is not supported in Little-Endian mode.
 775     If it is executed in Little-Endian mode, the system align-
 776     ment error handler is invoked.
 777
 778 Special Registers Altered:
 779
 780     None
 781