1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
3 <!-- This defines instructions that load from RAM to a register -->
5 <!-- Note that these pages also define equivalent store instructions, -->
6 <!-- these are described in fixedstore.mdwn -->
8 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
9 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
10 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
11 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
12 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
13 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
14 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
18 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
20 <!-- The byte, halfword, word, or doubleword in storage addressed by EA is loaded -->
21 <!-- into register RT. -->
23 <!-- Many of the Load instructions have an “update” form, in which register RA is -->
24 <!-- updated with the effective address. For these forms, if RA!=0 and RA!=RT, the -->
25 <!-- effective address is placed into register RA and the storage element (byte, -->
26 <!-- halfword, word, or doubleword) addressed by EA is loaded into RT. -->
39 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
43 Let the effective address (EA) be the sum (RA|0)+ D.
44 The byte in storage addressed by EA is loaded into
45 RT[56:63]. RT[0:55] are set to 0.
47 Special Registers Altered:
51 # Load Byte and Zero Indexed
61 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
65 Let the effective address (EA) be the sum
66 (RA|0)+ (RB). The byte in storage addressed by EA is
67 loaded into RT[56:63] . RT[0:55] are set to 0.
69 Special Registers Altered:
73 # Load Byte and Zero with Update
82 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
87 Let the effective address (EA) be the sum (RA)+ D. The
88 byte in storage addressed by EA is loaded into RT[56:63].
89 RT[0:55] are set to 0.
91 EA is placed into register RA.
93 If RA=0 or RA=RT, the instruction form is invalid.
95 Special Registers Altered:
99 # Load Byte and Zero with Update Indexed
108 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
113 Let the effective address (EA) be the sum (RA)+ (RB).
114 The byte in storage addressed by EA is loaded into
115 RT[56:63]. RT[0:55] are set to 0.
117 EA is placed into register RA.
119 If RA=0 or RA=RT, the instruction form is invalid.
121 Special Registers Altered:
125 # Load Halfword and Zero
135 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
139 Let the effective address (EA) be the sum (RA|0)+ D.
140 The halfword in storage addressed by EA is loaded into
141 RT[48:63]. RT[0:47] are set to 0.
143 Special Registers Altered:
147 # Load Halfword and Zero Indexed
157 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
161 Let the effective address (EA) be the sum
162 (RA|0)+ (RB). The halfword in storage addressed by
163 EA is loaded into RT[48:63]. RT[0:47] are set to 0.
165 Special Registers Altered:
169 # Load Halfword and Zero with Update
178 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
183 Let the effective address (EA) be the sum (RA)+ D. The
184 halfword in storage addressed by EA is loaded into
185 RT[48:63]. RT[0:47] are set to 0.
187 EA is placed into register RA.
189 If RA=0 or RA=RT, the instruction form is invalid.
191 Special Registers Altered:
195 # Load Halfword and Zero with Update Indexed
204 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
209 Let the effective address (EA) be the sum (RA)+ (RB).
210 The halfword in storage addressed by EA is loaded into
211 RT[48:63]. RT[0:47] are set to 0.
213 EA is placed into register RA.
215 If RA=0 or RA=RT, the instruction form is invalid.
217 Special Registers Altered:
221 # Load Halfword Algebraic
231 RT <- EXTS(MEM(EA, 2))
235 Let the effective address (EA) be the sum (RA|0)+ D.
236 The halfword in storage addressed by EA is loaded into
237 RT[48:63]. RT[0:47] are filled with a copy of bit 0 of the
240 Special Registers Altered:
244 # Load Halfword Algebraic Indexed
254 RT <- EXTS(MEM(EA, 2))
258 Let the effective address (EA) be the sum
259 (RA|0)+ (RB). The halfword in storage addressed by
260 EA is loaded into RT[48:63] . RT[0:47] are filled with a copy
261 of bit 0 of the loaded halfword.
263 Special Registers Altered:
267 # Load Halfword Algebraic with Update
276 RT <- EXTS(MEM(EA, 2))
281 Let the effective address (EA) be the sum (RA)+ D. The
282 halfword in storage addressed by EA is loaded into
283 RT[48:63]. RT[0:47] are filled with a copy of bit 0 of the
286 EA is placed into register RA.
288 If RA=0 or RA=RT, the instruction form is invalid.
290 Special Registers Altered:
294 # Load Halfword Algebraic with Update Indexed
303 RT <- EXTS(MEM(EA, 2))
308 Let the effective address (EA) be the sum (RA)+ (RB).
309 The halfword in storage addressed by EA is loaded into
310 RT[48:63]. RT[0:47] are filled with a copy of bit 0 of the
313 EA is placed into register RA.
315 If RA=0 or RA=RT, the instruction form is invalid.
317 Special Registers Altered:
331 RT <- [0] * 32 || MEM(EA, 4)
335 Let the effective address (EA) be the sum (RA|0)+ D.
336 The word in storage addressed by EA is loaded into
337 RT[32:63]. RT[0:31] are set to 0.
339 Special Registers Altered:
343 # Load Word and Zero Indexed
353 RT <- [0] * 32 || MEM(EA, 4)
357 Let the effective address (EA) be the sum
358 (RA|0)+ (RB). The word in storage addressed by EA is
359 loaded into RT[32:63] . RT[0:31] are set to 0.
361 Special Registers Altered:
365 # Load Word and Zero with Update
374 RT <- [0]*32 || MEM(EA, 4)
379 Let the effective address (EA) be the sum (RA)+ D. The
380 word in storage addressed by EA is loaded into
381 RT[32:63]. RT[0:31] are set to 0.
383 EA is placed into register RA.
385 If RA=0 or RA=RT, the instruction form is invalid.
387 Special Registers Altered:
391 # Load Word and Zero with Update Indexed
400 RT <- [0] * 32 || MEM(EA, 4)
405 Let the effective address (EA) be the sum (RA)+ (RB).
406 The word in storage addressed by EA is loaded into
407 RT[32:63]. RT[0:31] are set to 0.
409 EA is placed into register RA.
411 If RA=0 or RA=RT, the instruction form is invalid.
413 Special Registers Altered:
417 # Load Word Algebraic
426 EA <- b + EXTS(DS || 0b00)
427 RT <- EXTS(MEM(EA, 4))
431 Let the effective address (EA) be the sum
432 (RA|0)+ (DS||0b00). The word in storage addressed by
433 EA is loaded into RT[32:63] . RT[0:31] are filled with a copy
434 of bit 0 of the loaded word.
436 Special Registers Altered:
440 # Load Word Algebraic Indexed
450 RT <- EXTS(MEM(EA, 4))
454 Let the effective address (EA) be the sum
455 (RA|0)+ (RB). The word in storage addressed by EA is
456 loaded into RT[32:63] . RT[0:31] are filled with a copy of bit 0
459 Special Registers Altered:
463 # Load Word Algebraic with Update Indexed
472 RT <- EXTS(MEM(EA, 4))
477 Let the effective address (EA) be the sum (RA)+ (RB).
478 The word in storage addressed by EA is loaded into
479 RT[32:63]. RT[0:31] are filled with a copy of bit 0 of the
482 EA is placed into register RA.
484 If RA=0 or RA=RT, the instruction form is invalid.
486 Special Registers Altered:
499 EA <- b + EXTS(DS || 0b00)
504 Let the effective address (EA) be the sum
505 (RA|0)+ (DS||0b00). The doubleword in storage
506 addressed by EA is loaded into RT.
508 Special Registers Altered:
512 # Load Doubleword Indexed
526 Let the effective address (EA) be the sum
527 (RA|0)+ (RB). The doubleword in storage addressed by
528 EA is loaded into RT.
530 Special Registers Altered:
534 # Load Doubleword with Update Indexed
542 EA <- (RA) + EXTS(DS || 0b00)
548 Let the effective address (EA) be the sum
549 (RA)+ (DS||0b00). The doubleword in storage
550 addressed by EA is loaded into RT.
552 EA is placed into register RA.
554 If RA=0 or RA=RT, the instruction form is invalid.
556 Special Registers Altered:
560 # Load Doubleword with Update Indexed
574 Let the effective address (EA) be the sum (RA)+ (RB).
575 The doubleword in storage addressed by EA is loaded
578 EA is placed into register RA.
580 If RA=0 or RA=RT, the instruction form is invalid.
582 Special Registers Altered:
586 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
588 <!-- The contents of register RS are stored into the byte, halfword, word, or -->
589 <!-- doubleword in storage addressed by EA. -->
591 <!-- Many of the Store instructions have an “update” form, in which register RA is -->
592 <!-- updated with the effective address. For these forms, the following rules apply. -->
594 <!-- If RA!=0, the effective address is placed into register RA. -->
596 <!-- If RS=RA, the contents of register RS are copied to the target storage element -->
597 <!-- and then EA is placed into RA (RS). -->
599 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
601 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
603 <!-- For lq, the quadword in storage addressed by EA is loaded into an even-odd pair -->
604 <!-- of GPRs as follows. In Big-Endian mode, the even-numbered GPR is loaded with -->
605 <!-- the doubleword from storage addressed by EA and the odd-numbered GPR is loaded -->
606 <!-- with the doubleword addressed by EA+8. In Little-Endian mode, the even-numbered -->
607 <!-- GPR is loaded with the byte-reversed doubleword from storage addressed by EA+8 -->
608 <!-- and the odd-numbered GPR is loaded with the byte-reversed doubleword addressed -->
620 EA <- b + EXTS(DQ || 0b0000)
625 Let the effective address (EA) be the sum (RA|0)+
626 (DQ||0b0000). The quadword in storage addressed by
627 EA is loaded into register pair RTp.
629 If RTp is odd or RTp=RA, the instruction form is invalid.
630 If RTp=RA, an attempt to execute this instruction will
631 invoke the system illegal instruction error handler. (The
632 RTp=RA case includes the case of RTp=RA=0.)
634 The quadword in storage addressed by EA is loaded
635 into an even-odd pair of GPRs as follows. In
636 Big-Endian mode, the even-numbered GPR is loaded
637 with the doubleword from storage addressed by EA
638 and the odd-numbered GPR is loaded with the double-
639 word addressed by EA+8. In Little-Endian mode, the
640 even-numbered GPR is loaded with the byte-reversed
641 doubleword from storage addressed by EA+8 and the
642 odd-numbered GPR is loaded with the byte-reversed
643 doubleword addressed by EA.
645 Special Registers Altered:
649 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
651 # Load Halfword Byte-Reverse Indexed
661 load_data <- MEM(EA, 2)
662 RT <- [0]*48 || load_data[8:15] || load_data[0:7]
666 Let the effective address (EA) be the sum (RA|0)+(RB).
667 Bits 0:7 of the halfword in storage addressed by EA are
668 loaded into RT 56:63 . Bits 8:15 of the halfword in storage
669 addressed by EA are loaded into RT[48:55] . RT[0:47] are
672 Special Registers Altered:
676 # Load Word Byte-Reverse Indexed
686 load_data <- MEM(EA, 4)
687 RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
688 || load_data[8:15] || load_data[0:7])
692 Let the effective address (EA) be the sum
693 (RA|0)+ (RB). Bits 0:7 of the word in storage addressed
694 by EA are loaded into RT[56:63]. Bits 8:15 of the word in
695 storage addressed by EA are loaded into RT[48:55] . Bits
696 16:23 of the word in storage addressed by EA are
697 loaded into RT[40:47]. Bits 24:31 of the word in storage
698 addressed by EA are loaded into RT 32:39 . RT[0:31] are
701 Special Registers Altered:
706 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
708 # Load Doubleword Byte-Reverse Indexed
718 load_data <- MEM(EA, 8)
719 RT <- (load_data[56:63] || load_data[48:55]
720 || load_data[40:47] || load_data[32:39]
721 || load_data[24:31] || load_data[16:23]
722 || load_data[8:15] || load_data[0:7])
726 Let the effective address (EA) be the sum (RA|0)+(RB).
727 Bits 0:7 of the doubleword in storage addressed by EA
728 are loaded into RT[56:63] . Bits 8:15 of the doubleword in
729 storage addressed by EA are loaded into RT[48:55] . Bits
730 16:23 of the doubleword in storage addressed by EA
731 are loaded into RT[40:47]. Bits 24:31 of the doubleword in
732 storage addressed by EA are loaded into RT 32:39 . Bits
733 32:39 of the doubleword in storage addressed by EA
734 are loaded into RT[24:31]. Bits 40:47 of the doubleword in
735 storage addressed by EA are loaded into RT[16:23] . Bits
736 48:55 of the doubleword in storage addressed by EA
737 are loaded into RT[8:15] . Bits 56:63 of the doubleword in
738 storage addressed by EA are loaded into RT[0:7] .
740 Special Registers Altered:
744 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
758 GPR(r) <- [0]*32 || MEM(EA, 4)
764 Let n = (32-RT). Let the effective address (EA) be the
767 n consecutive words starting at EA are loaded into the
768 low-order 32 bits of GPRs RT through 31. The
769 high-order 32 bits of these GPRs are set to zero.
771 If RA is in the range of registers to be loaded, including
772 the case in which RA=0, the instruction form is invalid.
774 This instruction is not supported in Little-Endian mode.
775 If it is executed in Little-Endian mode, the system align-
776 ment error handler is invoked.
778 Special Registers Altered: