1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
3 <!-- This defines instructions that load from RAM to a register -->
5 <!-- Note that these pages also define equivalent store instructions, -->
6 <!-- these are described in fixedstore.mdwn -->
8 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
9 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
10 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
11 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
12 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
13 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
14 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
18 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
20 <!-- The byte, halfword, word, or doubleword in storage addressed by EA is loaded -->
21 <!-- into register RT. -->
23 <!-- Many of the Load instructions have an “update” form, in which register RA is -->
24 <!-- updated with the effective address. For these forms, if RA!=0 and RA!=RT, the -->
25 <!-- effective address is placed into register RA and the storage element (byte, -->
26 <!-- halfword, word, or doubleword) addressed by EA is loaded into RT. -->
39 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
43 Let the effective address (EA) be the sum (RA|0)+ D.
45 The byte in storage addressed by EA is loaded into RT[56:63].
46 RT[0:55] are set to 0.
48 Special Registers Altered:
52 # Load Byte and Zero Indexed
62 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
66 Let the effective address (EA) be the sum (RA|0)+ (RB).
68 The byte in storage addressed by EA is loaded into RT[56:63].
69 RT[0:55] are set to 0.
71 Special Registers Altered:
75 # Load Byte and Zero with Update
84 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
89 Let the effective address (EA) be the sum (RA)+ D.
91 The byte in storage addressed by EA is loaded into RT[56:63].
92 RT[0:55] are set to 0.
94 EA is placed into register RA.
96 If RA=0 or RA=RT, the instruction form is invalid.
98 Special Registers Altered:
102 # Load Byte and Zero with Update Indexed
111 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
116 Let the effective address (EA) be the sum (RA)+ (RB).
118 The byte in storage addressed by EA is loaded into RT[56:63].
119 RT[0:55] are set to 0.
121 EA is placed into register RA.
123 If RA=0 or RA=RT, the instruction form is invalid.
125 Special Registers Altered:
129 # Load Halfword and Zero
139 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
143 Let the effective address (EA) be the sum (RA|0)+ D.
145 The halfword in storage addressed by EA is loaded into RT[48:63].
146 RT[0:47] are set to 0.
148 Special Registers Altered:
152 # Load Halfword and Zero Indexed
162 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
166 Let the effective address (EA) be the sum (RA|0)+ (RB).
168 The halfword in storage addressed by EA is loaded into RT[48:63].
169 RT[0:47] are set to 0.
171 Special Registers Altered:
175 # Load Halfword and Zero with Update
184 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
189 Let the effective address (EA) be the sum (RA)+ D.
191 The halfword in storage addressed by EA is loaded into RT[48:63].
192 RT[0:47] are set to 0.
194 EA is placed into register RA.
196 If RA=0 or RA=RT, the instruction form is invalid.
198 Special Registers Altered:
202 # Load Halfword and Zero with Update Indexed
211 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
216 Let the effective address (EA) be the sum (RA)+ (RB).
218 The halfword in storage addressed by EA is loaded into RT[48:63].
219 RT[0:47] are set to 0.
221 EA is placed into register RA.
223 If RA=0 or RA=RT, the instruction form is invalid.
225 Special Registers Altered:
229 # Load Halfword Algebraic
239 RT <- EXTS(MEM(EA, 2))
243 Let the effective address (EA) be the sum (RA|0)+ D.
245 The halfword in storage addressed by EA is loaded into RT[48:63].
246 RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
248 Special Registers Altered:
252 # Load Halfword Algebraic Indexed
262 RT <- EXTS(MEM(EA, 2))
266 Let the effective address (EA) be the sum (RA|0)+ (RB).
268 The halfword in storage addressed by EA is loaded into RT[48:63].
269 RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
271 Special Registers Altered:
275 # Load Halfword Algebraic with Update
284 RT <- EXTS(MEM(EA, 2))
289 Let the effective address (EA) be the sum (RA)+ D.
290 The halfword in storage addressed by EA is loaded into RT[48:63].
291 RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
293 EA is placed into register RA.
295 If RA=0 or RA=RT, the instruction form is invalid.
297 Special Registers Altered:
301 # Load Halfword Algebraic with Update Indexed
310 RT <- EXTS(MEM(EA, 2))
315 Let the effective address (EA) be the sum (RA)+ (RB).
317 The halfword in storage addressed by EA is loaded into RT[48:63].
318 RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
320 EA is placed into register RA.
322 If RA=0 or RA=RT, the instruction form is invalid.
324 Special Registers Altered:
338 RT <- [0] * 32 || MEM(EA, 4)
342 Let the effective address (EA) be the sum (RA|0)+ D.
344 The word in storage addressed by EA is loaded into RT[32:63].
345 RT[0:31] are set to 0.
347 Special Registers Altered:
351 # Load Word and Zero Indexed
361 RT <- [0] * 32 || MEM(EA, 4)
365 Let the effective address (EA) be the sum (RA|0)+ (RB).
367 The word in storage addressed by EA is loaded into RT[32:63].
368 RT[0:31] are set to 0.
370 Special Registers Altered:
374 # Load Word and Zero with Update
383 RT <- [0]*32 || MEM(EA, 4)
388 Let the effective address (EA) be the sum (RA)+ D.
390 The word in storage addressed by EA is loaded into RT[32:63].
391 RT[0:31] are set to 0.
393 EA is placed into register RA.
395 If RA=0 or RA=RT, the instruction form is invalid.
397 Special Registers Altered:
401 # Load Word and Zero with Update Indexed
410 RT <- [0] * 32 || MEM(EA, 4)
415 Let the effective address (EA) be the sum (RA)+ (RB).
417 The word in storage addressed by EA is loaded into RT[32:63].
418 RT[0:31] are set to 0.
420 EA is placed into register RA.
422 If RA=0 or RA=RT, the instruction form is invalid.
424 Special Registers Altered:
428 # Load Word Algebraic
437 EA <- b + EXTS(DS || 0b00)
438 RT <- EXTS(MEM(EA, 4))
442 Let the effective address (EA) be the sum (RA|0)+ (DS||0b00).
444 The word in storage addressed by EA is loaded into RT[32:63].
445 RT[0:31] are filled with a copy of bit 0 of the loaded word.
447 Special Registers Altered:
451 # Load Word Algebraic Indexed
461 RT <- EXTS(MEM(EA, 4))
465 Let the effective address (EA) be the sum (RA|0)+ (RB).
467 The word in storage addressed by EA is loaded into RT[32:63].
468 RT[0:31] are filled with a copy of bit 0 of the loaded word.
470 Special Registers Altered:
474 # Load Word Algebraic with Update Indexed
483 RT <- EXTS(MEM(EA, 4))
488 Let the effective address (EA) be the sum (RA)+ (RB).
490 The word in storage addressed by EA is loaded into RT[32:63].
491 RT[0:31] are filled with a copy of bit 0 of the loaded word.
493 EA is placed into register RA.
495 If RA=0 or RA=RT, the instruction form is invalid.
497 Special Registers Altered:
510 EA <- b + EXTS(DS || 0b00)
515 Let the effective address (EA) be the sum (RA|0)+ (DS||0b00).
517 The doubleword in storage addressed by EA is loaded into RT.
519 Special Registers Altered:
523 # Load Doubleword Indexed
537 Let the effective address (EA) be the sum (RA|0)+ (RB).
539 The doubleword in storage addressed by EA is loaded into RT.
541 Special Registers Altered:
545 # Load Doubleword with Update Indexed
553 EA <- (RA) + EXTS(DS || 0b00)
559 Let the effective address (EA) be the sum (RA)+ (DS||0b00).
561 The doubleword in storage addressed by EA is loaded into RT.
563 EA is placed into register RA.
565 If RA=0 or RA=RT, the instruction form is invalid.
567 Special Registers Altered:
571 # Load Doubleword with Update Indexed
585 Let the effective address (EA) be the sum (RA)+ (RB).
587 The doubleword in storage addressed by EA is loaded into RT.
589 EA is placed into register RA.
591 If RA=0 or RA=RT, the instruction form is invalid.
593 Special Registers Altered:
597 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
599 <!-- The contents of register RS are stored into the byte, halfword, word, or -->
600 <!-- doubleword in storage addressed by EA. -->
602 <!-- Many of the Store instructions have an “update” form, in which register RA is -->
603 <!-- updated with the effective address. For these forms, the following rules apply. -->
605 <!-- If RA!=0, the effective address is placed into register RA. -->
607 <!-- If RS=RA, the contents of register RS are copied to the target storage element -->
608 <!-- and then EA is placed into RA (RS). -->
610 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
612 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
614 <!-- For lq, the quadword in storage addressed by EA is loaded into an even-odd pair -->
615 <!-- of GPRs as follows. In Big-Endian mode, the even-numbered GPR is loaded with -->
616 <!-- the doubleword from storage addressed by EA and the odd-numbered GPR is loaded -->
617 <!-- with the doubleword addressed by EA+8. In Little-Endian mode, the even-numbered -->
618 <!-- GPR is loaded with the byte-reversed doubleword from storage addressed by EA+8 -->
619 <!-- and the odd-numbered GPR is loaded with the byte-reversed doubleword addressed -->
631 EA <- b + EXTS(DQ || 0b0000)
636 Let the effective address (EA) be the sum (RA|0)+ (DQ||0b0000).
637 The quadword in storage addressed by EA is loaded into register pair RTp.
639 If RTp is odd or RTp=RA, the instruction form is invalid.
640 If RTp=RA, an attempt to execute this instruction will
641 invoke the system illegal instruction error handler. (The
642 RTp=RA case includes the case of RTp=RA=0.)
644 The quadword in storage addressed by EA is loaded
645 into an even-odd pair of GPRs as follows. In
646 Big-Endian mode, the even-numbered GPR is loaded
647 with the doubleword from storage addressed by EA
648 and the odd-numbered GPR is loaded with the double-
649 word addressed by EA+8. In Little-Endian mode, the
650 even-numbered GPR is loaded with the byte-reversed
651 doubleword from storage addressed by EA+8 and the
652 odd-numbered GPR is loaded with the byte-reversed
653 doubleword addressed by EA.
655 Special Registers Altered:
659 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
661 # Load Halfword Byte-Reverse Indexed
671 load_data <- MEM(EA, 2)
672 RT <- [0]*48 || load_data[8:15] || load_data[0:7]
676 Let the effective address (EA) be the sum (RA|0)+(RB).
678 Bits 0:7 of the halfword in storage addressed by EA are
679 loaded into RT 56:63 . Bits 8:15 of the halfword in storage
680 addressed by EA are loaded into RT[48:55].
681 RT[0:47] are set to 0.
683 Special Registers Altered:
687 # Load Word Byte-Reverse Indexed
697 load_data <- MEM(EA, 4)
698 RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
699 || load_data[8:15] || load_data[0:7])
703 Let the effective address (EA) be the sum (RA|0)+ (RB).
705 Bits 0:7 of the word in storage addressed
706 by EA are loaded into RT[56:63]. Bits 8:15 of the word in
707 storage addressed by EA are loaded into RT[48:55]. Bits
708 16:23 of the word in storage addressed by EA are
709 loaded into RT[40:47]. Bits 24:31 of the word in storage
710 addressed by EA are loaded into RT 32:39.
711 RT[0:31] are set to 0.
713 Special Registers Altered:
718 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
720 # Load Doubleword Byte-Reverse Indexed
730 load_data <- MEM(EA, 8)
731 RT <- (load_data[56:63] || load_data[48:55]
732 || load_data[40:47] || load_data[32:39]
733 || load_data[24:31] || load_data[16:23]
734 || load_data[8:15] || load_data[0:7])
738 Let the effective address (EA) be the sum (RA|0)+(RB).
740 Bits 0:7 of the doubleword in storage addressed by EA
741 are loaded into RT[56:63] . Bits 8:15 of the doubleword in
742 storage addressed by EA are loaded into RT[48:55] . Bits
743 16:23 of the doubleword in storage addressed by EA
744 are loaded into RT[40:47]. Bits 24:31 of the doubleword in
745 storage addressed by EA are loaded into RT 32:39 . Bits
746 32:39 of the doubleword in storage addressed by EA
747 are loaded into RT[24:31]. Bits 40:47 of the doubleword in
748 storage addressed by EA are loaded into RT[16:23] . Bits
749 48:55 of the doubleword in storage addressed by EA
750 are loaded into RT[8:15] . Bits 56:63 of the doubleword in
751 storage addressed by EA are loaded into RT[0:7] .
753 Special Registers Altered:
757 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
771 GPR(r) <- [0]*32 || MEM(EA, 4)
777 Let n = (32-RT). Let the effective address (EA) be the
780 n consecutive words starting at EA are loaded into the
781 low-order 32 bits of GPRs RT through 31. The
782 high-order 32 bits of these GPRs are set to zero.
784 If RA is in the range of registers to be loaded, including
785 the case in which RA=0, the instruction form is invalid.
787 This instruction is not supported in Little-Endian mode.
788 If it is executed in Little-Endian mode, the system align-
789 ment error handler is invoked.
791 Special Registers Altered: