openpower/isa/fixedload.mdwn

   1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
   2
   3 <!-- This defines instructions that load from RAM to a register -->
   4
   5 <!-- Note that these pages also define equivalent store instructions, -->
   6 <!-- these are described in fixedstore.mdwn -->
   7
   8 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
   9 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
  10 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
  11 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
  12 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
  13 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
  14 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
  15
  16
  17
  18 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
  19
  20 <!-- The byte, halfword, word, or doubleword in storage addressed by EA is loaded -->
  21 <!-- into register RT. -->
  22
  23 <!-- Many of the Load instructions have an “update” form, in which register RA is -->
  24 <!-- updated with the effective address. For these forms, if RA!=0 and RA!=RT, the -->
  25 <!-- effective address is placed into register RA and the storage element (byte, -->
  26 <!-- halfword, word, or doubleword) addressed by EA is loaded into RT. -->
  27
  28
  29 # Load Byte and Zero
  30
  31 D-Form
  32
  33 * lbz RT,D(RA)
  34
  35 Pseudo-code:
  36
  37     b <- (RA|0)
  38     EA <- b + EXTS(D)
  39     RT <- [0]*56 || MEM(EA, 1)
  40
  41 Special Registers Altered:
  42
  43     None
  44
  45 # Load Byte and Zero Indexed
  46
  47 X-Form
  48
  49 * lbzx RT,RA,RB
  50
  51 Pseudo-code:
  52
  53     b <- (RA|0)
  54     EA <- b + (RB)
  55     RT <- [0] * 56 || MEM(EA, 1)
  56
  57 Special Registers Altered:
  58
  59     None
  60
  61 # Load Byte and Zero with Update
  62
  63 D-Form
  64
  65 * lbzu RT,D(RA)
  66
  67 Pseudo-code:
  68
  69     EA <- (RA) + EXTS(D)
  70     RT <- [0] * 56 || MEM(EA, 1)
  71     RA <- EA
  72
  73 Special Registers Altered:
  74
  75     None
  76
  77 # Load Byte and Zero with Update Indexed
  78
  79 X-Form
  80
  81 * lbzux RT,RA,RB
  82
  83 Pseudo-code:
  84
  85     EA <- (RA) + (RB)
  86     RT <- [0] * 56 || MEM(EA, 1)
  87     RA <- EA
  88
  89 Special Registers Altered:
  90
  91     None
  92
  93 # Load Halfword and Zero
  94
  95 D-Form
  96
  97 * lhz RT,D(RA)
  98
  99 Pseudo-code:
 100
 101     b <- (RA|0)
 102     EA <- b + EXTS(D)
 103     RT <- [0] * 48 || MEM(EA, 2)
 104
 105 Special Registers Altered:
 106
 107     None
 108
 109 # Load Halfword and Zero Indexed
 110
 111 X-Form
 112
 113 * lhzx RT,RA,RB
 114
 115 Pseudo-code:
 116
 117     b <- (RA|0)
 118     EA <- b + (RB)
 119     RT <- [0] * 48 || MEM(EA, 2)
 120
 121 Special Registers Altered:
 122
 123     None
 124
 125 # Load Halfword and Zero with Update
 126
 127 D-Form
 128
 129 * lhzu RT,D(RA)
 130
 131 Pseudo-code:
 132
 133     EA <- (RA) + EXTS(D)
 134     RT <- [0] * 48 || MEM(EA, 2)
 135     RA <- EA
 136
 137 Special Registers Altered:
 138
 139     None
 140
 141 # Load Halfword and Zero with Update Indexed
 142
 143 X-Form
 144
 145 * lhzux RT,RA,RB
 146
 147 Pseudo-code:
 148
 149     EA <- (RA) + (RB)
 150     RT <- [0] * 48 || MEM(EA, 2)
 151     RA <- EA
 152
 153 Special Registers Altered:
 154
 155     None
 156
 157 # Load Halfword Algebraic
 158
 159 D-Form
 160
 161 * lha RT,D(RA)
 162
 163 Pseudo-code:
 164
 165     b <- (RA|0)
 166     EA <- b + EXTS(D)
 167     RT <- EXTS(MEM(EA, 2))
 168
 169 Special Registers Altered:
 170
 171     None
 172
 173 # Load Halfword Algebraic Indexed
 174
 175 X-Form
 176
 177 * lhax RT,RA,RB
 178
 179 Pseudo-code:
 180
 181     b <- (RA|0)
 182     EA <- b + (RB)
 183     RT <- EXTS(MEM(EA, 2))
 184
 185 Special Registers Altered:
 186
 187     None
 188
 189 # Load Halfword Algebraic with Update
 190
 191 D-Form
 192
 193 * lhau RT,D(RA)
 194
 195 Pseudo-code:
 196
 197     EA <- (RA) + EXTS(D)
 198     RT <- EXTS(MEM(EA, 2))
 199     RA <- EA
 200
 201 Special Registers Altered:
 202
 203     None
 204
 205 # Load Halfword Algebraic with Update Indexed
 206
 207 X-Form
 208
 209 * lhaux RT,RA,RB
 210
 211 Pseudo-code:
 212
 213     EA <- (RA) + (RB)
 214     RT <- EXTS(MEM(EA, 2))
 215     RA <- EA
 216
 217 Special Registers Altered:
 218
 219     None
 220
 221 # Load Word and Zero
 222
 223 D-Form
 224
 225 * lwz RT,D(RA)
 226
 227 Pseudo-code:
 228
 229     b <- (RA|0)
 230     EA <- b + EXTS(D)
 231     RT <- [0] * 32 || MEM(EA, 4)
 232
 233 Special Registers Altered:
 234
 235     None
 236
 237 # Load Word and Zero Indexed
 238
 239 X-Form
 240
 241 * lwzx RT,RA,RB
 242
 243 Pseudo-code:
 244
 245     b <- (RA|0)
 246     EA <- b + (RB)
 247     RT <- [0] * 32 || MEM(EA, 4)
 248
 249 Special Registers Altered:
 250
 251     None
 252
 253 # Load Word and Zero with Update
 254
 255 D-Form
 256
 257 * lwzu RT,D(RA)
 258
 259 Pseudo-code:
 260
 261     EA <- (RA) + EXTS(D)
 262     RT <- [0]*32 || MEM(EA, 4)
 263     RA <- EA
 264
 265 Special Registers Altered:
 266
 267     None
 268
 269 # Load Word and Zero with Update Indexed
 270
 271 X-Form
 272
 273 * lwzux RT,RA,RB
 274
 275 Pseudo-code:
 276
 277     EA <- (RA) + (RB)
 278     RT <- [0] * 32 || MEM(EA, 4)
 279     RA <- EA
 280
 281 Special Registers Altered:
 282
 283     None
 284
 285 # Load Word Algebraic
 286
 287 DS-Form
 288
 289 * lwa RT,DS(RA)
 290
 291 Pseudo-code:
 292
 293     b <- (RA|0)
 294     EA <- b + EXTS(DS || 0b00)
 295     RT <- EXTS(MEM(EA, 4))
 296
 297 Special Registers Altered:
 298
 299     None
 300
 301 # Load Word Algebraic Indexed
 302
 303 X-Form
 304
 305 * lwax RT,RA,RB
 306
 307 Pseudo-code:
 308
 309     b <- (RA|0)
 310     EA <- b + (RB)
 311     RT <- EXTS(MEM(EA, 4))
 312
 313 Special Registers Altered:
 314
 315     None
 316
 317 # Load Word Algebraic with Update Indexed
 318
 319 X-Form
 320
 321 * lwaux RT,RA,RB
 322
 323 Pseudo-code:
 324
 325     EA <- (RA) + (RB)
 326     RT <- EXTS(MEM(EA, 4))
 327     RA <- EA
 328
 329 Special Registers Altered:
 330
 331     None
 332
 333 # Load Doubleword
 334
 335 DS-Form
 336
 337 * ld RT,DS(RA)
 338
 339 Pseudo-code:
 340
 341     b <- (RA|0)
 342     EA <- b + EXTS(DS || 0b00)
 343     RT <- MEM(EA, 8)
 344
 345 Special Registers Altered:
 346
 347     None
 348
 349 # Load Doubleword Indexed
 350
 351 X-Form
 352
 353 * ldx RT,RA,RB
 354
 355 Pseudo-code:
 356
 357     b <- (RA|0)
 358     EA <- b + (RB)
 359     RT <- MEM(EA, 8)
 360
 361 Special Registers Altered:
 362
 363     None
 364
 365 # Load Doubleword with Update Indexed
 366
 367 DS-Form
 368
 369 * ldu RT,DS(RA)
 370
 371 Pseudo-code:
 372
 373     EA <- (RA) + EXTS(DS || 0b00)
 374     RT <- MEM(EA, 8)
 375     RA <- EA
 376
 377 Special Registers Altered:
 378
 379     None
 380
 381 # Load Doubleword with Update Indexed
 382
 383 X-Form
 384
 385 * ldux RT,RA,RB
 386
 387 Pseudo-code:
 388
 389     EA <- (RA) + (RB)
 390     RT <- MEM(EA, 8)
 391     RA <- EA
 392
 393 Special Registers Altered:
 394
 395     None
 396
 397 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
 398
 399 <!-- The contents of register RS are stored into the byte, halfword, word, or -->
 400 <!-- doubleword in storage addressed by EA. -->
 401
 402 <!-- Many of the Store instructions have an “update” form, in which register RA is -->
 403 <!-- updated with the effective address. For these forms, the following rules apply. -->
 404
 405 <!-- If RA!=0, the effective address is placed into register RA. -->
 406
 407 <!-- If RS=RA, the contents of register RS are copied to the target storage element -->
 408 <!-- and then EA is placed into RA (RS). -->
 409
 410 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
 411
 412 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
 413
 414 <!-- For lq, the quadword in storage addressed by EA is loaded into an even-odd pair -->
 415 <!-- of GPRs as follows. In Big-Endian mode, the even-numbered GPR is loaded with -->
 416 <!-- the doubleword from storage addressed by EA and the odd-numbered GPR is loaded -->
 417 <!-- with the doubleword addressed by EA+8. In Little-Endian mode, the even-numbered -->
 418 <!-- GPR is loaded with the byte-reversed doubleword from storage addressed by EA+8 -->
 419 <!-- and the odd-numbered GPR is loaded with the byte-reversed doubleword addressed -->
 420 <!-- by EA. -->
 421
 422 # Load Quadword
 423
 424 DQ-Form
 425
 426 * lq RTp,DQ(RA)
 427
 428 Pseudo-code:
 429
 430     b <- (RA|0)
 431     EA <- b + EXTS(DQ || 0b0000)
 432     RTp <- MEM(EA, 16)
 433
 434 Special Registers Altered:
 435
 436     None
 437
 438 <!-- MISSING stq -->
 439
 440 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
 441
 442 # Load Halfword Byte-Reverse Indexed
 443
 444 X-Form
 445
 446 * lhbrx RT,RA,RB
 447
 448 Pseudo-code:
 449
 450     b <- (RA|0)
 451     EA <- b + (RB)
 452     load_data <- MEM(EA, 2)
 453     RT <- [0]*48 || load_data[8:15] || load_data[0:7]
 454
 455 Special Registers Altered:
 456
 457     None
 458
 459 <!-- MISSING sthbrx -->
 460
 461 # Load Word Byte-Reverse Indexed
 462
 463 X-Form
 464
 465 * lwbrx RT,RA,RB
 466
 467 Pseudo-code:
 468
 469     b <- (RA|0)
 470     EA <- b + (RB)
 471     load_data <- MEM(EA, 4)
 472     RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
 473                     || load_data[8:15]  || load_data[0:7])
 474
 475 Special Registers Altered:
 476
 477     None
 478
 479 <!-- MISSING stwbrx -->
 480
 481
 482 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
 483
 484 # Load Doubleword Byte-Reverse Indexed
 485
 486 X-Form
 487
 488 * ldbrx RT,RA,RB
 489
 490 Pseudo-code:
 491
 492     b <- (RA|0)
 493     EA <- b + (RB)
 494     load_data <- MEM(EA, 8)
 495     RT <- (load_data[56:63] || load_data[48:55]
 496         || load_data[40:47] || load_data[32:39]
 497         || load_data[24:31] || load_data[16:23]
 498         || load_data[8:15]  || load_data[0:7])
 499
 500 Special Registers Altered:
 501
 502     None
 503
 504 <!-- MISSING stdbrx -->
 505
 506 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
 507
 508 # Load Multiple Word
 509
 510 DQ-Form
 511
 512 * lmw RT,D(RA)
 513
 514 Pseudo-code:
 515
 516     b <- (RA|0)
 517     EA <- b + EXTS(D)
 518     r <- RT
 519     do while r <=  31
 520         GPR(r) <- [0]*32 || MEM(EA, 4)
 521         r <- r + 1
 522         EA <- EA + 4
 523
 524 Special Registers Altered:
 525
 526     None
 527
 528 <!-- MISSING stmw -->
 529
 530