1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
3 <!-- This defines instructions that load from RAM to a register -->
5 <!-- Note that these pages also define equivalent store instructions, -->
6 <!-- these are described in fixedstore.mdwn -->
8 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
9 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
10 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
11 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
12 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
13 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
14 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
18 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
20 <!-- The byte, halfword, word, or doubleword in storage addressed by EA is loaded -->
21 <!-- into register RT. -->
23 <!-- Many of the Load instructions have an “update” form, in which register RA is -->
24 <!-- updated with the effective address. For these forms, if RA!=0 and RA!=RT, the -->
25 <!-- effective address is placed into register RA and the storage element (byte, -->
26 <!-- halfword, word, or doubleword) addressed by EA is loaded into RT. -->
39 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
43 Let the effective address (EA) be the sum (RA|0)+ D.
44 The byte in storage addressed by EA is loaded into
45 RT[56:63]. RT[0:55] are set to 0.
47 Special Registers Altered:
51 # Load Byte and Zero Indexed
61 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
63 Special Registers Altered:
67 # Load Byte and Zero with Update
76 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
79 Special Registers Altered:
83 # Load Byte and Zero with Update Indexed
92 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
95 Description:Let the effective address (EA) be the sum (RA)+ (RB).
96 The byte in storage addressed by EA is loaded into
97 RT56:63. RT0:55 are set to 0.
98 EA is placed into register RA.
99 If RA=0 or RA=RT, the instruction form is invalid.
101 Special Registers Altered:
105 # Load Halfword and Zero
115 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
117 Special Registers Altered:
121 # Load Halfword and Zero Indexed
131 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
133 Special Registers Altered:
137 # Load Halfword and Zero with Update
146 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
149 Special Registers Altered:
153 # Load Halfword and Zero with Update Indexed
162 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
165 Special Registers Altered:
169 # Load Halfword Algebraic
179 RT <- EXTS(MEM(EA, 2))
181 Special Registers Altered:
185 # Load Halfword Algebraic Indexed
195 RT <- EXTS(MEM(EA, 2))
197 Special Registers Altered:
201 # Load Halfword Algebraic with Update
210 RT <- EXTS(MEM(EA, 2))
213 Special Registers Altered:
217 # Load Halfword Algebraic with Update Indexed
226 RT <- EXTS(MEM(EA, 2))
229 Special Registers Altered:
243 RT <- [0] * 32 || MEM(EA, 4)
245 Special Registers Altered:
249 # Load Word and Zero Indexed
259 RT <- [0] * 32 || MEM(EA, 4)
261 Special Registers Altered:
265 # Load Word and Zero with Update
274 RT <- [0]*32 || MEM(EA, 4)
277 Special Registers Altered:
281 # Load Word and Zero with Update Indexed
290 RT <- [0] * 32 || MEM(EA, 4)
293 Special Registers Altered:
297 # Load Word Algebraic
306 EA <- b + EXTS(DS || 0b00)
307 RT <- EXTS(MEM(EA, 4))
309 Special Registers Altered:
313 # Load Word Algebraic Indexed
323 RT <- EXTS(MEM(EA, 4))
325 Special Registers Altered:
329 # Load Word Algebraic with Update Indexed
338 RT <- EXTS(MEM(EA, 4))
341 Special Registers Altered:
354 EA <- b + EXTS(DS || 0b00)
357 Special Registers Altered:
361 # Load Doubleword Indexed
373 Special Registers Altered:
377 # Load Doubleword with Update Indexed
385 EA <- (RA) + EXTS(DS || 0b00)
389 Special Registers Altered:
393 # Load Doubleword with Update Indexed
405 Special Registers Altered:
409 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
411 <!-- The contents of register RS are stored into the byte, halfword, word, or -->
412 <!-- doubleword in storage addressed by EA. -->
414 <!-- Many of the Store instructions have an “update” form, in which register RA is -->
415 <!-- updated with the effective address. For these forms, the following rules apply. -->
417 <!-- If RA!=0, the effective address is placed into register RA. -->
419 <!-- If RS=RA, the contents of register RS are copied to the target storage element -->
420 <!-- and then EA is placed into RA (RS). -->
422 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
424 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
426 <!-- For lq, the quadword in storage addressed by EA is loaded into an even-odd pair -->
427 <!-- of GPRs as follows. In Big-Endian mode, the even-numbered GPR is loaded with -->
428 <!-- the doubleword from storage addressed by EA and the odd-numbered GPR is loaded -->
429 <!-- with the doubleword addressed by EA+8. In Little-Endian mode, the even-numbered -->
430 <!-- GPR is loaded with the byte-reversed doubleword from storage addressed by EA+8 -->
431 <!-- and the odd-numbered GPR is loaded with the byte-reversed doubleword addressed -->
443 EA <- b + EXTS(DQ || 0b0000)
446 Special Registers Altered:
450 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
452 # Load Halfword Byte-Reverse Indexed
462 load_data <- MEM(EA, 2)
463 RT <- [0]*48 || load_data[8:15] || load_data[0:7]
465 Special Registers Altered:
469 # Load Word Byte-Reverse Indexed
479 load_data <- MEM(EA, 4)
480 RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
481 || load_data[8:15] || load_data[0:7])
483 Special Registers Altered:
488 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
490 # Load Doubleword Byte-Reverse Indexed
500 load_data <- MEM(EA, 8)
501 RT <- (load_data[56:63] || load_data[48:55]
502 || load_data[40:47] || load_data[32:39]
503 || load_data[24:31] || load_data[16:23]
504 || load_data[8:15] || load_data[0:7])
506 Special Registers Altered:
510 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
524 GPR(r) <- [0]*32 || MEM(EA, 4)
528 Special Registers Altered: