openpower/isa/fixedload.mdwn

   1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
   2
   3 <!-- This defines instructions that load from RAM to a register -->
   4
   5 <!-- Note that these pages also define equivalent store instructions, -->
   6 <!-- these are described in fixedstore.mdwn -->
   7
   8 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
   9 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
  10 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
  11 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
  12 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
  13 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
  14 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
  15
  16
  17
  18 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
  19
  20 <!-- The byte, halfword, word, or doubleword in storage addressed by EA is loaded -->
  21 <!-- into register RT. -->
  22
  23 <!-- Many of the Load instructions have an “update” form, in which register RA is -->
  24 <!-- updated with the effective address. For these forms, if RA!=0 and RA!=RT, the -->
  25 <!-- effective address is placed into register RA and the storage element (byte, -->
  26 <!-- halfword, word, or doubleword) addressed by EA is loaded into RT. -->
  27
  28
  29 # Load Byte and Zero
  30
  31 D-Form
  32
  33 * lbz RT,D(RA)
  34
  35 Pseudo-code:
  36
  37     b <- (RA|0)
  38     EA <- b + EXTS(D)
  39     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  40
  41 Description:
  42
  43     Let the effective address (EA) be the sum (RA|0)+ D.
  44     The byte in storage addressed by EA is loaded into
  45     RT[56:63]. RT[0:55] are set to 0.
  46
  47 Special Registers Altered:
  48
  49     None
  50
  51 # Load Byte and Zero Indexed
  52
  53 X-Form
  54
  55 * lbzx RT,RA,RB
  56
  57 Pseudo-code:
  58
  59     b <- (RA|0)
  60     EA <- b + (RB)
  61     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  62
  63 Special Registers Altered:
  64
  65     None
  66
  67 # Load Byte and Zero with Update
  68
  69 D-Form
  70
  71 * lbzu RT,D(RA)
  72
  73 Pseudo-code:
  74
  75     EA <- (RA) + EXTS(D)
  76     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  77     RA <- EA
  78
  79 Description:
  80
  81     Let the effective address (EA) be the sum (RA)+ D. The
  82     byte in storage addressed by EA is loaded into RT[56:63].
  83     RT[0:55] are set to 0.
  84
  85     EA is placed into register RA.
  86
  87     If RA=0 or RA=RT, the instruction form is invalid.
  88
  89 Special Registers Altered:
  90
  91     None
  92
  93 # Load Byte and Zero with Update Indexed
  94
  95 X-Form
  96
  97 * lbzux RT,RA,RB
  98
  99 Pseudo-code:
 100
 101     EA <- (RA) + (RB)
 102     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
 103     RA <- EA
 104
 105 Description:
 106
 107     Let the effective address (EA) be the sum (RA)+ (RB).
 108     The byte in storage addressed by EA is loaded into
 109     RT[56:63]. RT[0:55] are set to 0.
 110
 111     EA is placed into register RA.
 112
 113     If RA=0 or RA=RT, the instruction form is invalid.
 114
 115 Special Registers Altered:
 116
 117     None
 118
 119 # Load Halfword and Zero
 120
 121 D-Form
 122
 123 * lhz RT,D(RA)
 124
 125 Pseudo-code:
 126
 127     b <- (RA|0)
 128     EA <- b + EXTS(D)
 129     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 130
 131 Special Registers Altered:
 132
 133     None
 134
 135 # Load Halfword and Zero Indexed
 136
 137 X-Form
 138
 139 * lhzx RT,RA,RB
 140
 141 Pseudo-code:
 142
 143     b <- (RA|0)
 144     EA <- b + (RB)
 145     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 146
 147 Special Registers Altered:
 148
 149     None
 150
 151 # Load Halfword and Zero with Update
 152
 153 D-Form
 154
 155 * lhzu RT,D(RA)
 156
 157 Pseudo-code:
 158
 159     EA <- (RA) + EXTS(D)
 160     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 161     RA <- EA
 162
 163 Description:
 164
 165     Let the effective address (EA) be the sum (RA)+ D. The
 166     halfword in storage addressed by EA is loaded into
 167     RT[48:63]. RT[0:47] are set to 0.
 168
 169     EA is placed into register RA.
 170
 171     If RA=0 or RA=RT, the instruction form is invalid.
 172
 173 Special Registers Altered:
 174
 175     None
 176
 177 # Load Halfword and Zero with Update Indexed
 178
 179 X-Form
 180
 181 * lhzux RT,RA,RB
 182
 183 Pseudo-code:
 184
 185     EA <- (RA) + (RB)
 186     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 187     RA <- EA
 188
 189 Description:
 190
 191     Let the effective address (EA) be the sum (RA)+ (RB).
 192     The halfword in storage addressed by EA is loaded into
 193     RT[48:63]. RT[0:47] are set to 0.
 194
 195     EA is placed into register RA.
 196
 197     If RA=0 or RA=RT, the instruction form is invalid.
 198
 199 Special Registers Altered:
 200
 201     None
 202
 203 # Load Halfword Algebraic
 204
 205 D-Form
 206
 207 * lha RT,D(RA)
 208
 209 Pseudo-code:
 210
 211     b <- (RA|0)
 212     EA <- b + EXTS(D)
 213     RT <- EXTS(MEM(EA, 2))
 214
 215 Special Registers Altered:
 216
 217     None
 218
 219 # Load Halfword Algebraic Indexed
 220
 221 X-Form
 222
 223 * lhax RT,RA,RB
 224
 225 Pseudo-code:
 226
 227     b <- (RA|0)
 228     EA <- b + (RB)
 229     RT <- EXTS(MEM(EA, 2))
 230
 231 Special Registers Altered:
 232
 233     None
 234
 235 # Load Halfword Algebraic with Update
 236
 237 D-Form
 238
 239 * lhau RT,D(RA)
 240
 241 Pseudo-code:
 242
 243     EA <- (RA) + EXTS(D)
 244     RT <- EXTS(MEM(EA, 2))
 245     RA <- EA
 246
 247 Description:
 248
 249     Let the effective address (EA) be the sum (RA)+ D. The
 250     halfword in storage addressed by EA is loaded into
 251     RT[48:63]. RT[0:47] are filled with a copy of bit 0 of the
 252     loaded halfword.
 253
 254     EA is placed into register RA.
 255
 256     If RA=0 or RA=RT, the instruction form is invalid.
 257
 258 Special Registers Altered:
 259
 260     None
 261
 262 # Load Halfword Algebraic with Update Indexed
 263
 264 X-Form
 265
 266 * lhaux RT,RA,RB
 267
 268 Pseudo-code:
 269
 270     EA <- (RA) + (RB)
 271     RT <- EXTS(MEM(EA, 2))
 272     RA <- EA
 273
 274 Special Registers Altered:
 275
 276     None
 277
 278 # Load Word and Zero
 279
 280 D-Form
 281
 282 * lwz RT,D(RA)
 283
 284 Pseudo-code:
 285
 286     b <- (RA|0)
 287     EA <- b + EXTS(D)
 288     RT <- [0] * 32 || MEM(EA, 4)
 289
 290 Special Registers Altered:
 291
 292     None
 293
 294 # Load Word and Zero Indexed
 295
 296 X-Form
 297
 298 * lwzx RT,RA,RB
 299
 300 Pseudo-code:
 301
 302     b <- (RA|0)
 303     EA <- b + (RB)
 304     RT <- [0] * 32 || MEM(EA, 4)
 305
 306 Special Registers Altered:
 307
 308     None
 309
 310 # Load Word and Zero with Update
 311
 312 D-Form
 313
 314 * lwzu RT,D(RA)
 315
 316 Pseudo-code:
 317
 318     EA <- (RA) + EXTS(D)
 319     RT <- [0]*32 || MEM(EA, 4)
 320     RA <- EA
 321
 322 Special Registers Altered:
 323
 324     None
 325
 326 # Load Word and Zero with Update Indexed
 327
 328 X-Form
 329
 330 * lwzux RT,RA,RB
 331
 332 Pseudo-code:
 333
 334     EA <- (RA) + (RB)
 335     RT <- [0] * 32 || MEM(EA, 4)
 336     RA <- EA
 337
 338 Special Registers Altered:
 339
 340     None
 341
 342 # Load Word Algebraic
 343
 344 DS-Form
 345
 346 * lwa RT,DS(RA)
 347
 348 Pseudo-code:
 349
 350     b <- (RA|0)
 351     EA <- b + EXTS(DS || 0b00)
 352     RT <- EXTS(MEM(EA, 4))
 353
 354 Special Registers Altered:
 355
 356     None
 357
 358 # Load Word Algebraic Indexed
 359
 360 X-Form
 361
 362 * lwax RT,RA,RB
 363
 364 Pseudo-code:
 365
 366     b <- (RA|0)
 367     EA <- b + (RB)
 368     RT <- EXTS(MEM(EA, 4))
 369
 370 Special Registers Altered:
 371
 372     None
 373
 374 # Load Word Algebraic with Update Indexed
 375
 376 X-Form
 377
 378 * lwaux RT,RA,RB
 379
 380 Pseudo-code:
 381
 382     EA <- (RA) + (RB)
 383     RT <- EXTS(MEM(EA, 4))
 384     RA <- EA
 385
 386 Special Registers Altered:
 387
 388     None
 389
 390 # Load Doubleword
 391
 392 DS-Form
 393
 394 * ld RT,DS(RA)
 395
 396 Pseudo-code:
 397
 398     b <- (RA|0)
 399     EA <- b + EXTS(DS || 0b00)
 400     RT <- MEM(EA, 8)
 401
 402 Special Registers Altered:
 403
 404     None
 405
 406 # Load Doubleword Indexed
 407
 408 X-Form
 409
 410 * ldx RT,RA,RB
 411
 412 Pseudo-code:
 413
 414     b <- (RA|0)
 415     EA <- b + (RB)
 416     RT <- MEM(EA, 8)
 417
 418 Special Registers Altered:
 419
 420     None
 421
 422 # Load Doubleword with Update Indexed
 423
 424 DS-Form
 425
 426 * ldu RT,DS(RA)
 427
 428 Pseudo-code:
 429
 430     EA <- (RA) + EXTS(DS || 0b00)
 431     RT <- MEM(EA, 8)
 432     RA <- EA
 433
 434 Special Registers Altered:
 435
 436     None
 437
 438 # Load Doubleword with Update Indexed
 439
 440 X-Form
 441
 442 * ldux RT,RA,RB
 443
 444 Pseudo-code:
 445
 446     EA <- (RA) + (RB)
 447     RT <- MEM(EA, 8)
 448     RA <- EA
 449
 450 Special Registers Altered:
 451
 452     None
 453
 454 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
 455
 456 <!-- The contents of register RS are stored into the byte, halfword, word, or -->
 457 <!-- doubleword in storage addressed by EA. -->
 458
 459 <!-- Many of the Store instructions have an “update” form, in which register RA is -->
 460 <!-- updated with the effective address. For these forms, the following rules apply. -->
 461
 462 <!-- If RA!=0, the effective address is placed into register RA. -->
 463
 464 <!-- If RS=RA, the contents of register RS are copied to the target storage element -->
 465 <!-- and then EA is placed into RA (RS). -->
 466
 467 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
 468
 469 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
 470
 471 <!-- For lq, the quadword in storage addressed by EA is loaded into an even-odd pair -->
 472 <!-- of GPRs as follows. In Big-Endian mode, the even-numbered GPR is loaded with -->
 473 <!-- the doubleword from storage addressed by EA and the odd-numbered GPR is loaded -->
 474 <!-- with the doubleword addressed by EA+8. In Little-Endian mode, the even-numbered -->
 475 <!-- GPR is loaded with the byte-reversed doubleword from storage addressed by EA+8 -->
 476 <!-- and the odd-numbered GPR is loaded with the byte-reversed doubleword addressed -->
 477 <!-- by EA. -->
 478
 479 # Load Quadword
 480
 481 DQ-Form
 482
 483 * lq RTp,DQ(RA)
 484
 485 Pseudo-code:
 486
 487     b <- (RA|0)
 488     EA <- b + EXTS(DQ || 0b0000)
 489     RTp <- MEM(EA, 16)
 490
 491 Special Registers Altered:
 492
 493     None
 494
 495 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
 496
 497 # Load Halfword Byte-Reverse Indexed
 498
 499 X-Form
 500
 501 * lhbrx RT,RA,RB
 502
 503 Pseudo-code:
 504
 505     b <- (RA|0)
 506     EA <- b + (RB)
 507     load_data <- MEM(EA, 2)
 508     RT <- [0]*48 || load_data[8:15] || load_data[0:7]
 509
 510 Special Registers Altered:
 511
 512     None
 513
 514 # Load Word Byte-Reverse Indexed
 515
 516 X-Form
 517
 518 * lwbrx RT,RA,RB
 519
 520 Pseudo-code:
 521
 522     b <- (RA|0)
 523     EA <- b + (RB)
 524     load_data <- MEM(EA, 4)
 525     RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
 526                     || load_data[8:15]  || load_data[0:7])
 527
 528 Special Registers Altered:
 529
 530     None
 531
 532
 533 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
 534
 535 # Load Doubleword Byte-Reverse Indexed
 536
 537 X-Form
 538
 539 * ldbrx RT,RA,RB
 540
 541 Pseudo-code:
 542
 543     b <- (RA|0)
 544     EA <- b + (RB)
 545     load_data <- MEM(EA, 8)
 546     RT <- (load_data[56:63] || load_data[48:55]
 547         || load_data[40:47] || load_data[32:39]
 548         || load_data[24:31] || load_data[16:23]
 549         || load_data[8:15]  || load_data[0:7])
 550
 551 Special Registers Altered:
 552
 553     None
 554
 555 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
 556
 557 # Load Multiple Word
 558
 559 DQ-Form
 560
 561 * lmw RT,D(RA)
 562
 563 Pseudo-code:
 564
 565     b <- (RA|0)
 566     EA <- b + EXTS(D)
 567     r <- RT[0:63]
 568     do while r <=  31
 569         GPR(r) <- [0]*32 || MEM(EA, 4)
 570         r <- r + 1
 571         EA <- EA + 4
 572
 573 Special Registers Altered:
 574
 575     None
 576