openpower/isa/fixedload.mdwn

   1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
   2
   3 <!-- This defines instructions that load from RAM to a register -->
   4
   5 <!-- Note that these pages also define equivalent store instructions, -->
   6 <!-- these are described in fixedstore.mdwn -->
   7
   8 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
   9 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
  10 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
  11 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
  12 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
  13 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
  14 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
  15
  16
  17
  18 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
  19
  20 <!-- The byte, halfword, word, or doubleword in storage addressed by EA is loaded -->
  21 <!-- into register RT. -->
  22
  23 <!-- Many of the Load instructions have an “update” form, in which register RA is -->
  24 <!-- updated with the effective address. For these forms, if RA!=0 and RA!=RT, the -->
  25 <!-- effective address is placed into register RA and the storage element (byte, -->
  26 <!-- halfword, word, or doubleword) addressed by EA is loaded into RT. -->
  27
  28
  29 # Load Byte and Zero
  30
  31 D-Form
  32
  33 * lbz RT,D(RA)
  34
  35 Pseudo-code:
  36
  37     b <- (RA|0)
  38     EA <- b + EXTS(D)
  39     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  40
  41 Description:
  42
  43     Let the effective address (EA) be the sum (RA|0)+ D.
  44     The byte in storage addressed by EA is loaded into
  45     RT[56:63]. RT[0:55] are set to 0.
  46
  47 Special Registers Altered:
  48
  49     None
  50
  51 # Load Byte and Zero Indexed
  52
  53 X-Form
  54
  55 * lbzx RT,RA,RB
  56
  57 Pseudo-code:
  58
  59     b <- (RA|0)
  60     EA <- b + (RB)
  61     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  62
  63 Description:
  64
  65     Let the effective address (EA) be the sum
  66     (RA|0)+ (RB). The byte in storage addressed by EA is
  67     loaded into RT[56:63] . RT[0:55] are set to 0.
  68
  69 Special Registers Altered:
  70
  71     None
  72
  73 # Load Byte and Zero with Update
  74
  75 D-Form
  76
  77 * lbzu RT,D(RA)
  78
  79 Pseudo-code:
  80
  81     EA <- (RA) + EXTS(D)
  82     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  83     RA <- EA
  84
  85 Description:
  86
  87     Let the effective address (EA) be the sum (RA)+ D. The
  88     byte in storage addressed by EA is loaded into RT[56:63].
  89     RT[0:55] are set to 0.
  90
  91     EA is placed into register RA.
  92
  93     If RA=0 or RA=RT, the instruction form is invalid.
  94
  95 Special Registers Altered:
  96
  97     None
  98
  99 # Load Byte and Zero with Update Indexed
 100
 101 X-Form
 102
 103 * lbzux RT,RA,RB
 104
 105 Pseudo-code:
 106
 107     EA <- (RA) + (RB)
 108     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
 109     RA <- EA
 110
 111 Description:
 112
 113     Let the effective address (EA) be the sum (RA)+ (RB).
 114     The byte in storage addressed by EA is loaded into
 115     RT[56:63]. RT[0:55] are set to 0.
 116
 117     EA is placed into register RA.
 118
 119     If RA=0 or RA=RT, the instruction form is invalid.
 120
 121 Special Registers Altered:
 122
 123     None
 124
 125 # Load Halfword and Zero
 126
 127 D-Form
 128
 129 * lhz RT,D(RA)
 130
 131 Pseudo-code:
 132
 133     b <- (RA|0)
 134     EA <- b + EXTS(D)
 135     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 136
 137 Special Registers Altered:
 138
 139     None
 140
 141 # Load Halfword and Zero Indexed
 142
 143 X-Form
 144
 145 * lhzx RT,RA,RB
 146
 147 Pseudo-code:
 148
 149     b <- (RA|0)
 150     EA <- b + (RB)
 151     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 152
 153 Special Registers Altered:
 154
 155     None
 156
 157 # Load Halfword and Zero with Update
 158
 159 D-Form
 160
 161 * lhzu RT,D(RA)
 162
 163 Pseudo-code:
 164
 165     EA <- (RA) + EXTS(D)
 166     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 167     RA <- EA
 168
 169 Description:
 170
 171     Let the effective address (EA) be the sum (RA)+ D. The
 172     halfword in storage addressed by EA is loaded into
 173     RT[48:63]. RT[0:47] are set to 0.
 174
 175     EA is placed into register RA.
 176
 177     If RA=0 or RA=RT, the instruction form is invalid.
 178
 179 Special Registers Altered:
 180
 181     None
 182
 183 # Load Halfword and Zero with Update Indexed
 184
 185 X-Form
 186
 187 * lhzux RT,RA,RB
 188
 189 Pseudo-code:
 190
 191     EA <- (RA) + (RB)
 192     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 193     RA <- EA
 194
 195 Description:
 196
 197     Let the effective address (EA) be the sum (RA)+ (RB).
 198     The halfword in storage addressed by EA is loaded into
 199     RT[48:63]. RT[0:47] are set to 0.
 200
 201     EA is placed into register RA.
 202
 203     If RA=0 or RA=RT, the instruction form is invalid.
 204
 205 Special Registers Altered:
 206
 207     None
 208
 209 # Load Halfword Algebraic
 210
 211 D-Form
 212
 213 * lha RT,D(RA)
 214
 215 Pseudo-code:
 216
 217     b <- (RA|0)
 218     EA <- b + EXTS(D)
 219     RT <- EXTS(MEM(EA, 2))
 220
 221 Special Registers Altered:
 222
 223     None
 224
 225 # Load Halfword Algebraic Indexed
 226
 227 X-Form
 228
 229 * lhax RT,RA,RB
 230
 231 Pseudo-code:
 232
 233     b <- (RA|0)
 234     EA <- b + (RB)
 235     RT <- EXTS(MEM(EA, 2))
 236
 237 Special Registers Altered:
 238
 239     None
 240
 241 # Load Halfword Algebraic with Update
 242
 243 D-Form
 244
 245 * lhau RT,D(RA)
 246
 247 Pseudo-code:
 248
 249     EA <- (RA) + EXTS(D)
 250     RT <- EXTS(MEM(EA, 2))
 251     RA <- EA
 252
 253 Description:
 254
 255     Let the effective address (EA) be the sum (RA)+ D. The
 256     halfword in storage addressed by EA is loaded into
 257     RT[48:63]. RT[0:47] are filled with a copy of bit 0 of the
 258     loaded halfword.
 259
 260     EA is placed into register RA.
 261
 262     If RA=0 or RA=RT, the instruction form is invalid.
 263
 264 Special Registers Altered:
 265
 266     None
 267
 268 # Load Halfword Algebraic with Update Indexed
 269
 270 X-Form
 271
 272 * lhaux RT,RA,RB
 273
 274 Pseudo-code:
 275
 276     EA <- (RA) + (RB)
 277     RT <- EXTS(MEM(EA, 2))
 278     RA <- EA
 279
 280 Description:
 281
 282     Let the effective address (EA) be the sum (RA)+ (RB).
 283     The halfword in storage addressed by EA is loaded into
 284     RT48:63. RT 0:47 are filled with a copy of bit 0 of the
 285     loaded halfword.
 286
 287     EA is placed into register RA.
 288
 289     If RA=0 or RA=RT, the instruction form is invalid.
 290
 291 Special Registers Altered:
 292
 293     None
 294
 295 # Load Word and Zero
 296
 297 D-Form
 298
 299 * lwz RT,D(RA)
 300
 301 Pseudo-code:
 302
 303     b <- (RA|0)
 304     EA <- b + EXTS(D)
 305     RT <- [0] * 32 || MEM(EA, 4)
 306
 307 Special Registers Altered:
 308
 309     None
 310
 311 # Load Word and Zero Indexed
 312
 313 X-Form
 314
 315 * lwzx RT,RA,RB
 316
 317 Pseudo-code:
 318
 319     b <- (RA|0)
 320     EA <- b + (RB)
 321     RT <- [0] * 32 || MEM(EA, 4)
 322
 323 Special Registers Altered:
 324
 325     None
 326
 327 # Load Word and Zero with Update
 328
 329 D-Form
 330
 331 * lwzu RT,D(RA)
 332
 333 Pseudo-code:
 334
 335     EA <- (RA) + EXTS(D)
 336     RT <- [0]*32 || MEM(EA, 4)
 337     RA <- EA
 338
 339 Special Registers Altered:
 340
 341     None
 342
 343 # Load Word and Zero with Update Indexed
 344
 345 X-Form
 346
 347 * lwzux RT,RA,RB
 348
 349 Pseudo-code:
 350
 351     EA <- (RA) + (RB)
 352     RT <- [0] * 32 || MEM(EA, 4)
 353     RA <- EA
 354
 355 Special Registers Altered:
 356
 357     None
 358
 359 # Load Word Algebraic
 360
 361 DS-Form
 362
 363 * lwa RT,DS(RA)
 364
 365 Pseudo-code:
 366
 367     b <- (RA|0)
 368     EA <- b + EXTS(DS || 0b00)
 369     RT <- EXTS(MEM(EA, 4))
 370
 371 Special Registers Altered:
 372
 373     None
 374
 375 # Load Word Algebraic Indexed
 376
 377 X-Form
 378
 379 * lwax RT,RA,RB
 380
 381 Pseudo-code:
 382
 383     b <- (RA|0)
 384     EA <- b + (RB)
 385     RT <- EXTS(MEM(EA, 4))
 386
 387 Special Registers Altered:
 388
 389     None
 390
 391 # Load Word Algebraic with Update Indexed
 392
 393 X-Form
 394
 395 * lwaux RT,RA,RB
 396
 397 Pseudo-code:
 398
 399     EA <- (RA) + (RB)
 400     RT <- EXTS(MEM(EA, 4))
 401     RA <- EA
 402
 403 Special Registers Altered:
 404
 405     None
 406
 407 # Load Doubleword
 408
 409 DS-Form
 410
 411 * ld RT,DS(RA)
 412
 413 Pseudo-code:
 414
 415     b <- (RA|0)
 416     EA <- b + EXTS(DS || 0b00)
 417     RT <- MEM(EA, 8)
 418
 419 Special Registers Altered:
 420
 421     None
 422
 423 # Load Doubleword Indexed
 424
 425 X-Form
 426
 427 * ldx RT,RA,RB
 428
 429 Pseudo-code:
 430
 431     b <- (RA|0)
 432     EA <- b + (RB)
 433     RT <- MEM(EA, 8)
 434
 435 Special Registers Altered:
 436
 437     None
 438
 439 # Load Doubleword with Update Indexed
 440
 441 DS-Form
 442
 443 * ldu RT,DS(RA)
 444
 445 Pseudo-code:
 446
 447     EA <- (RA) + EXTS(DS || 0b00)
 448     RT <- MEM(EA, 8)
 449     RA <- EA
 450
 451 Special Registers Altered:
 452
 453     None
 454
 455 # Load Doubleword with Update Indexed
 456
 457 X-Form
 458
 459 * ldux RT,RA,RB
 460
 461 Pseudo-code:
 462
 463     EA <- (RA) + (RB)
 464     RT <- MEM(EA, 8)
 465     RA <- EA
 466
 467 Special Registers Altered:
 468
 469     None
 470
 471 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
 472
 473 <!-- The contents of register RS are stored into the byte, halfword, word, or -->
 474 <!-- doubleword in storage addressed by EA. -->
 475
 476 <!-- Many of the Store instructions have an “update” form, in which register RA is -->
 477 <!-- updated with the effective address. For these forms, the following rules apply. -->
 478
 479 <!-- If RA!=0, the effective address is placed into register RA. -->
 480
 481 <!-- If RS=RA, the contents of register RS are copied to the target storage element -->
 482 <!-- and then EA is placed into RA (RS). -->
 483
 484 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
 485
 486 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
 487
 488 <!-- For lq, the quadword in storage addressed by EA is loaded into an even-odd pair -->
 489 <!-- of GPRs as follows. In Big-Endian mode, the even-numbered GPR is loaded with -->
 490 <!-- the doubleword from storage addressed by EA and the odd-numbered GPR is loaded -->
 491 <!-- with the doubleword addressed by EA+8. In Little-Endian mode, the even-numbered -->
 492 <!-- GPR is loaded with the byte-reversed doubleword from storage addressed by EA+8 -->
 493 <!-- and the odd-numbered GPR is loaded with the byte-reversed doubleword addressed -->
 494 <!-- by EA. -->
 495
 496 # Load Quadword
 497
 498 DQ-Form
 499
 500 * lq RTp,DQ(RA)
 501
 502 Pseudo-code:
 503
 504     b <- (RA|0)
 505     EA <- b + EXTS(DQ || 0b0000)
 506     RTp <- MEM(EA, 16)
 507
 508 Special Registers Altered:
 509
 510     None
 511
 512 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
 513
 514 # Load Halfword Byte-Reverse Indexed
 515
 516 X-Form
 517
 518 * lhbrx RT,RA,RB
 519
 520 Pseudo-code:
 521
 522     b <- (RA|0)
 523     EA <- b + (RB)
 524     load_data <- MEM(EA, 2)
 525     RT <- [0]*48 || load_data[8:15] || load_data[0:7]
 526
 527 Special Registers Altered:
 528
 529     None
 530
 531 # Load Word Byte-Reverse Indexed
 532
 533 X-Form
 534
 535 * lwbrx RT,RA,RB
 536
 537 Pseudo-code:
 538
 539     b <- (RA|0)
 540     EA <- b + (RB)
 541     load_data <- MEM(EA, 4)
 542     RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
 543                     || load_data[8:15]  || load_data[0:7])
 544
 545 Special Registers Altered:
 546
 547     None
 548
 549
 550 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
 551
 552 # Load Doubleword Byte-Reverse Indexed
 553
 554 X-Form
 555
 556 * ldbrx RT,RA,RB
 557
 558 Pseudo-code:
 559
 560     b <- (RA|0)
 561     EA <- b + (RB)
 562     load_data <- MEM(EA, 8)
 563     RT <- (load_data[56:63] || load_data[48:55]
 564         || load_data[40:47] || load_data[32:39]
 565         || load_data[24:31] || load_data[16:23]
 566         || load_data[8:15]  || load_data[0:7])
 567
 568 Special Registers Altered:
 569
 570     None
 571
 572 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
 573
 574 # Load Multiple Word
 575
 576 DQ-Form
 577
 578 * lmw RT,D(RA)
 579
 580 Pseudo-code:
 581
 582     b <- (RA|0)
 583     EA <- b + EXTS(D)
 584     r <- RT[0:63]
 585     do while r <=  31
 586         GPR(r) <- [0]*32 || MEM(EA, 4)
 587         r <- r + 1
 588         EA <- EA + 4
 589
 590 Special Registers Altered:
 591
 592     None
 593