openpower/isa/fixedload.mdwn

   1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
   2
   3 <!-- This defines instructions that load from RAM to a register -->
   4
   5 <!-- Note that these pages also define equivalent store instructions, -->
   6 <!-- these are described in fixedstore.mdwn -->
   7
   8 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
   9 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
  10 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
  11 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
  12 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
  13 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
  14 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
  15
  16
  17
  18 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
  19
  20 <!-- The byte, halfword, word, or doubleword in storage addressed by EA is loaded -->
  21 <!-- into register RT. -->
  22
  23 <!-- Many of the Load instructions have an “update” form, in which register RA is -->
  24 <!-- updated with the effective address. For these forms, if RA!=0 and RA!=RT, the -->
  25 <!-- effective address is placed into register RA and the storage element (byte, -->
  26 <!-- halfword, word, or doubleword) addressed by EA is loaded into RT. -->
  27
  28
  29 # Load Byte and Zero
  30
  31 D-Form
  32
  33 * lbz RT,D(RA)
  34
  35 Pseudo-code:
  36
  37     b <- (RA|0)
  38     EA <- b + EXTS(D)
  39     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  40
  41 Description:
  42
  43 Let the effective address (EA) be the sum (RA|0)+ D.
  44 The byte in storage addressed by EA is loaded into
  45 RT[56:63]. RT[0:55] are set to 0.
  46
  47 Special Registers Altered:
  48
  49     None
  50
  51 # Load Byte and Zero Indexed
  52
  53 X-Form
  54
  55 * lbzx RT,RA,RB
  56
  57 Pseudo-code:
  58
  59     b <- (RA|0)
  60     EA <- b + (RB)
  61     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  62
  63 Special Registers Altered:
  64
  65     None
  66
  67 # Load Byte and Zero with Update
  68
  69 D-Form
  70
  71 * lbzu RT,D(RA)
  72
  73 Pseudo-code:
  74
  75     EA <- (RA) + EXTS(D)
  76     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  77     RA <- EA
  78
  79 Description:Let the effective address (EA) be the sum (RA)+ D. The
  80 byte in storage addressed by EA is loaded into RT 56:63.
  81 RT0:55 are set to 0.
  82 EA is placed into register RA.
  83 If RA=0 or RA=RT, the instruction form is invalid.
  84
  85 Special Registers Altered:
  86
  87     None
  88
  89 # Load Byte and Zero with Update Indexed
  90
  91 X-Form
  92
  93 * lbzux RT,RA,RB
  94
  95 Pseudo-code:
  96
  97     EA <- (RA) + (RB)
  98     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  99     RA <- EA
 100
 101 Description:Let the effective address (EA) be the sum (RA)+ (RB).
 102 The byte in storage addressed by EA is loaded into
 103 RT56:63. RT0:55 are set to 0.
 104 EA is placed into register RA.
 105 If RA=0 or RA=RT, the instruction form is invalid.
 106
 107 Special Registers Altered:
 108
 109     None
 110
 111 # Load Halfword and Zero
 112
 113 D-Form
 114
 115 * lhz RT,D(RA)
 116
 117 Pseudo-code:
 118
 119     b <- (RA|0)
 120     EA <- b + EXTS(D)
 121     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 122
 123 Special Registers Altered:
 124
 125     None
 126
 127 # Load Halfword and Zero Indexed
 128
 129 X-Form
 130
 131 * lhzx RT,RA,RB
 132
 133 Pseudo-code:
 134
 135     b <- (RA|0)
 136     EA <- b + (RB)
 137     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 138
 139 Special Registers Altered:
 140
 141     None
 142
 143 # Load Halfword and Zero with Update
 144
 145 D-Form
 146
 147 * lhzu RT,D(RA)
 148
 149 Pseudo-code:
 150
 151     EA <- (RA) + EXTS(D)
 152     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 153     RA <- EA
 154
 155 Description:Let the effective address (EA) be the sum (RA)+ D. The
 156 halfword in storage addressed by EA is loaded into
 157 RT48:63. RT 0:47 are set to 0.
 158 EA is placed into register RA.
 159 If RA=0 or RA=RT, the instruction form is invalid.
 160
 161 Special Registers Altered:
 162
 163     None
 164
 165 # Load Halfword and Zero with Update Indexed
 166
 167 X-Form
 168
 169 * lhzux RT,RA,RB
 170
 171 Pseudo-code:
 172
 173     EA <- (RA) + (RB)
 174     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 175     RA <- EA
 176
 177 Special Registers Altered:
 178
 179     None
 180
 181 # Load Halfword Algebraic
 182
 183 D-Form
 184
 185 * lha RT,D(RA)
 186
 187 Pseudo-code:
 188
 189     b <- (RA|0)
 190     EA <- b + EXTS(D)
 191     RT <- EXTS(MEM(EA, 2))
 192
 193 Special Registers Altered:
 194
 195     None
 196
 197 # Load Halfword Algebraic Indexed
 198
 199 X-Form
 200
 201 * lhax RT,RA,RB
 202
 203 Pseudo-code:
 204
 205     b <- (RA|0)
 206     EA <- b + (RB)
 207     RT <- EXTS(MEM(EA, 2))
 208
 209 Special Registers Altered:
 210
 211     None
 212
 213 # Load Halfword Algebraic with Update
 214
 215 D-Form
 216
 217 * lhau RT,D(RA)
 218
 219 Pseudo-code:
 220
 221     EA <- (RA) + EXTS(D)
 222     RT <- EXTS(MEM(EA, 2))
 223     RA <- EA
 224
 225 Special Registers Altered:
 226
 227     None
 228
 229 # Load Halfword Algebraic with Update Indexed
 230
 231 X-Form
 232
 233 * lhaux RT,RA,RB
 234
 235 Pseudo-code:
 236
 237     EA <- (RA) + (RB)
 238     RT <- EXTS(MEM(EA, 2))
 239     RA <- EA
 240
 241 Special Registers Altered:
 242
 243     None
 244
 245 # Load Word and Zero
 246
 247 D-Form
 248
 249 * lwz RT,D(RA)
 250
 251 Pseudo-code:
 252
 253     b <- (RA|0)
 254     EA <- b + EXTS(D)
 255     RT <- [0] * 32 || MEM(EA, 4)
 256
 257 Special Registers Altered:
 258
 259     None
 260
 261 # Load Word and Zero Indexed
 262
 263 X-Form
 264
 265 * lwzx RT,RA,RB
 266
 267 Pseudo-code:
 268
 269     b <- (RA|0)
 270     EA <- b + (RB)
 271     RT <- [0] * 32 || MEM(EA, 4)
 272
 273 Special Registers Altered:
 274
 275     None
 276
 277 # Load Word and Zero with Update
 278
 279 D-Form
 280
 281 * lwzu RT,D(RA)
 282
 283 Pseudo-code:
 284
 285     EA <- (RA) + EXTS(D)
 286     RT <- [0]*32 || MEM(EA, 4)
 287     RA <- EA
 288
 289 Special Registers Altered:
 290
 291     None
 292
 293 # Load Word and Zero with Update Indexed
 294
 295 X-Form
 296
 297 * lwzux RT,RA,RB
 298
 299 Pseudo-code:
 300
 301     EA <- (RA) + (RB)
 302     RT <- [0] * 32 || MEM(EA, 4)
 303     RA <- EA
 304
 305 Special Registers Altered:
 306
 307     None
 308
 309 # Load Word Algebraic
 310
 311 DS-Form
 312
 313 * lwa RT,DS(RA)
 314
 315 Pseudo-code:
 316
 317     b <- (RA|0)
 318     EA <- b + EXTS(DS || 0b00)
 319     RT <- EXTS(MEM(EA, 4))
 320
 321 Special Registers Altered:
 322
 323     None
 324
 325 # Load Word Algebraic Indexed
 326
 327 X-Form
 328
 329 * lwax RT,RA,RB
 330
 331 Pseudo-code:
 332
 333     b <- (RA|0)
 334     EA <- b + (RB)
 335     RT <- EXTS(MEM(EA, 4))
 336
 337 Special Registers Altered:
 338
 339     None
 340
 341 # Load Word Algebraic with Update Indexed
 342
 343 X-Form
 344
 345 * lwaux RT,RA,RB
 346
 347 Pseudo-code:
 348
 349     EA <- (RA) + (RB)
 350     RT <- EXTS(MEM(EA, 4))
 351     RA <- EA
 352
 353 Special Registers Altered:
 354
 355     None
 356
 357 # Load Doubleword
 358
 359 DS-Form
 360
 361 * ld RT,DS(RA)
 362
 363 Pseudo-code:
 364
 365     b <- (RA|0)
 366     EA <- b + EXTS(DS || 0b00)
 367     RT <- MEM(EA, 8)
 368
 369 Special Registers Altered:
 370
 371     None
 372
 373 # Load Doubleword Indexed
 374
 375 X-Form
 376
 377 * ldx RT,RA,RB
 378
 379 Pseudo-code:
 380
 381     b <- (RA|0)
 382     EA <- b + (RB)
 383     RT <- MEM(EA, 8)
 384
 385 Special Registers Altered:
 386
 387     None
 388
 389 # Load Doubleword with Update Indexed
 390
 391 DS-Form
 392
 393 * ldu RT,DS(RA)
 394
 395 Pseudo-code:
 396
 397     EA <- (RA) + EXTS(DS || 0b00)
 398     RT <- MEM(EA, 8)
 399     RA <- EA
 400
 401 Special Registers Altered:
 402
 403     None
 404
 405 # Load Doubleword with Update Indexed
 406
 407 X-Form
 408
 409 * ldux RT,RA,RB
 410
 411 Pseudo-code:
 412
 413     EA <- (RA) + (RB)
 414     RT <- MEM(EA, 8)
 415     RA <- EA
 416
 417 Special Registers Altered:
 418
 419     None
 420
 421 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
 422
 423 <!-- The contents of register RS are stored into the byte, halfword, word, or -->
 424 <!-- doubleword in storage addressed by EA. -->
 425
 426 <!-- Many of the Store instructions have an “update” form, in which register RA is -->
 427 <!-- updated with the effective address. For these forms, the following rules apply. -->
 428
 429 <!-- If RA!=0, the effective address is placed into register RA. -->
 430
 431 <!-- If RS=RA, the contents of register RS are copied to the target storage element -->
 432 <!-- and then EA is placed into RA (RS). -->
 433
 434 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
 435
 436 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
 437
 438 <!-- For lq, the quadword in storage addressed by EA is loaded into an even-odd pair -->
 439 <!-- of GPRs as follows. In Big-Endian mode, the even-numbered GPR is loaded with -->
 440 <!-- the doubleword from storage addressed by EA and the odd-numbered GPR is loaded -->
 441 <!-- with the doubleword addressed by EA+8. In Little-Endian mode, the even-numbered -->
 442 <!-- GPR is loaded with the byte-reversed doubleword from storage addressed by EA+8 -->
 443 <!-- and the odd-numbered GPR is loaded with the byte-reversed doubleword addressed -->
 444 <!-- by EA. -->
 445
 446 # Load Quadword
 447
 448 DQ-Form
 449
 450 * lq RTp,DQ(RA)
 451
 452 Pseudo-code:
 453
 454     b <- (RA|0)
 455     EA <- b + EXTS(DQ || 0b0000)
 456     RTp <- MEM(EA, 16)
 457
 458 Special Registers Altered:
 459
 460     None
 461
 462 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
 463
 464 # Load Halfword Byte-Reverse Indexed
 465
 466 X-Form
 467
 468 * lhbrx RT,RA,RB
 469
 470 Pseudo-code:
 471
 472     b <- (RA|0)
 473     EA <- b + (RB)
 474     load_data <- MEM(EA, 2)
 475     RT <- [0]*48 || load_data[8:15] || load_data[0:7]
 476
 477 Special Registers Altered:
 478
 479     None
 480
 481 # Load Word Byte-Reverse Indexed
 482
 483 X-Form
 484
 485 * lwbrx RT,RA,RB
 486
 487 Pseudo-code:
 488
 489     b <- (RA|0)
 490     EA <- b + (RB)
 491     load_data <- MEM(EA, 4)
 492     RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
 493                     || load_data[8:15]  || load_data[0:7])
 494
 495 Special Registers Altered:
 496
 497     None
 498
 499
 500 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
 501
 502 # Load Doubleword Byte-Reverse Indexed
 503
 504 X-Form
 505
 506 * ldbrx RT,RA,RB
 507
 508 Pseudo-code:
 509
 510     b <- (RA|0)
 511     EA <- b + (RB)
 512     load_data <- MEM(EA, 8)
 513     RT <- (load_data[56:63] || load_data[48:55]
 514         || load_data[40:47] || load_data[32:39]
 515         || load_data[24:31] || load_data[16:23]
 516         || load_data[8:15]  || load_data[0:7])
 517
 518 Special Registers Altered:
 519
 520     None
 521
 522 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
 523
 524 # Load Multiple Word
 525
 526 DQ-Form
 527
 528 * lmw RT,D(RA)
 529
 530 Pseudo-code:
 531
 532     b <- (RA|0)
 533     EA <- b + EXTS(D)
 534     r <- RT[0:63]
 535     do while r <=  31
 536         GPR(r) <- [0]*32 || MEM(EA, 4)
 537         r <- r + 1
 538         EA <- EA + 4
 539
 540 Special Registers Altered:
 541
 542     None
 543