openpower/isa/fixedload.mdwn

   1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
   2
   3 <!-- This defines instructions that load from RAM to a register -->
   4
   5 <!-- Note that these pages also define equivalent store instructions, -->
   6 <!-- these are described in fixedstore.mdwn -->
   7
   8 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
   9 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
  10 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
  11 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
  12 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
  13 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
  14 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
  15
  16
  17
  18 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
  19
  20 <!-- The byte, halfword, word, or doubleword in storage addressed by EA is loaded -->
  21 <!-- into register RT. -->
  22
  23 <!-- Many of the Load instructions have an “update” form, in which register RA is -->
  24 <!-- updated with the effective address. For these forms, if RA!=0 and RA!=RT, the -->
  25 <!-- effective address is placed into register RA and the storage element (byte, -->
  26 <!-- halfword, word, or doubleword) addressed by EA is loaded into RT. -->
  27
  28
  29 # Load Byte and Zero
  30
  31 D-Form
  32
  33 * lbz RT,D(RA)
  34
  35 Pseudo-code:
  36
  37     b <- (RA|0)
  38     EA <- b + EXTS(D)
  39     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  40
  41 Description:
  42
  43     Let the effective address (EA) be the sum (RA|0)+ D.
  44     The byte in storage addressed by EA is loaded into
  45     RT[56:63]. RT[0:55] are set to 0.
  46
  47 Special Registers Altered:
  48
  49     None
  50
  51 # Load Byte and Zero Indexed
  52
  53 X-Form
  54
  55 * lbzx RT,RA,RB
  56
  57 Pseudo-code:
  58
  59     b <- (RA|0)
  60     EA <- b + (RB)
  61     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  62
  63 Special Registers Altered:
  64
  65     None
  66
  67 # Load Byte and Zero with Update
  68
  69 D-Form
  70
  71 * lbzu RT,D(RA)
  72
  73 Pseudo-code:
  74
  75     EA <- (RA) + EXTS(D)
  76     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  77     RA <- EA
  78
  79 Description:
  80
  81     Let the effective address (EA) be the sum (RA)+ D. The
  82     byte in storage addressed by EA is loaded into RT[56:63].
  83     RT[0:55] are set to 0.
  84
  85     EA is placed into register RA.
  86
  87     If RA=0 or RA=RT, the instruction form is invalid.
  88
  89 Special Registers Altered:
  90
  91     None
  92
  93 # Load Byte and Zero with Update Indexed
  94
  95 X-Form
  96
  97 * lbzux RT,RA,RB
  98
  99 Pseudo-code:
 100
 101     EA <- (RA) + (RB)
 102     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
 103     RA <- EA
 104
 105 Description:
 106
 107     Let the effective address (EA) be the sum (RA)+ (RB).
 108     The byte in storage addressed by EA is loaded into
 109     RT[56:63]. RT[0:55] are set to 0.
 110
 111     EA is placed into register RA.
 112
 113     If RA=0 or RA=RT, the instruction form is invalid.
 114
 115 Special Registers Altered:
 116
 117     None
 118
 119 # Load Halfword and Zero
 120
 121 D-Form
 122
 123 * lhz RT,D(RA)
 124
 125 Pseudo-code:
 126
 127     b <- (RA|0)
 128     EA <- b + EXTS(D)
 129     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 130
 131 Special Registers Altered:
 132
 133     None
 134
 135 # Load Halfword and Zero Indexed
 136
 137 X-Form
 138
 139 * lhzx RT,RA,RB
 140
 141 Pseudo-code:
 142
 143     b <- (RA|0)
 144     EA <- b + (RB)
 145     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 146
 147 Special Registers Altered:
 148
 149     None
 150
 151 # Load Halfword and Zero with Update
 152
 153 D-Form
 154
 155 * lhzu RT,D(RA)
 156
 157 Pseudo-code:
 158
 159     EA <- (RA) + EXTS(D)
 160     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 161     RA <- EA
 162
 163 Description:
 164
 165     Let the effective address (EA) be the sum (RA)+ D. The
 166     halfword in storage addressed by EA is loaded into
 167     RT[48:63]. RT[0:47] are set to 0.
 168
 169     EA is placed into register RA.
 170
 171     If RA=0 or RA=RT, the instruction form is invalid.
 172
 173 Special Registers Altered:
 174
 175     None
 176
 177 # Load Halfword and Zero with Update Indexed
 178
 179 X-Form
 180
 181 * lhzux RT,RA,RB
 182
 183 Pseudo-code:
 184
 185     EA <- (RA) + (RB)
 186     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 187     RA <- EA
 188
 189 Special Registers Altered:
 190
 191     None
 192
 193 # Load Halfword Algebraic
 194
 195 D-Form
 196
 197 * lha RT,D(RA)
 198
 199 Pseudo-code:
 200
 201     b <- (RA|0)
 202     EA <- b + EXTS(D)
 203     RT <- EXTS(MEM(EA, 2))
 204
 205 Special Registers Altered:
 206
 207     None
 208
 209 # Load Halfword Algebraic Indexed
 210
 211 X-Form
 212
 213 * lhax RT,RA,RB
 214
 215 Pseudo-code:
 216
 217     b <- (RA|0)
 218     EA <- b + (RB)
 219     RT <- EXTS(MEM(EA, 2))
 220
 221 Special Registers Altered:
 222
 223     None
 224
 225 # Load Halfword Algebraic with Update
 226
 227 D-Form
 228
 229 * lhau RT,D(RA)
 230
 231 Pseudo-code:
 232
 233     EA <- (RA) + EXTS(D)
 234     RT <- EXTS(MEM(EA, 2))
 235     RA <- EA
 236
 237 Special Registers Altered:
 238
 239     None
 240
 241 # Load Halfword Algebraic with Update Indexed
 242
 243 X-Form
 244
 245 * lhaux RT,RA,RB
 246
 247 Pseudo-code:
 248
 249     EA <- (RA) + (RB)
 250     RT <- EXTS(MEM(EA, 2))
 251     RA <- EA
 252
 253 Special Registers Altered:
 254
 255     None
 256
 257 # Load Word and Zero
 258
 259 D-Form
 260
 261 * lwz RT,D(RA)
 262
 263 Pseudo-code:
 264
 265     b <- (RA|0)
 266     EA <- b + EXTS(D)
 267     RT <- [0] * 32 || MEM(EA, 4)
 268
 269 Special Registers Altered:
 270
 271     None
 272
 273 # Load Word and Zero Indexed
 274
 275 X-Form
 276
 277 * lwzx RT,RA,RB
 278
 279 Pseudo-code:
 280
 281     b <- (RA|0)
 282     EA <- b + (RB)
 283     RT <- [0] * 32 || MEM(EA, 4)
 284
 285 Special Registers Altered:
 286
 287     None
 288
 289 # Load Word and Zero with Update
 290
 291 D-Form
 292
 293 * lwzu RT,D(RA)
 294
 295 Pseudo-code:
 296
 297     EA <- (RA) + EXTS(D)
 298     RT <- [0]*32 || MEM(EA, 4)
 299     RA <- EA
 300
 301 Special Registers Altered:
 302
 303     None
 304
 305 # Load Word and Zero with Update Indexed
 306
 307 X-Form
 308
 309 * lwzux RT,RA,RB
 310
 311 Pseudo-code:
 312
 313     EA <- (RA) + (RB)
 314     RT <- [0] * 32 || MEM(EA, 4)
 315     RA <- EA
 316
 317 Special Registers Altered:
 318
 319     None
 320
 321 # Load Word Algebraic
 322
 323 DS-Form
 324
 325 * lwa RT,DS(RA)
 326
 327 Pseudo-code:
 328
 329     b <- (RA|0)
 330     EA <- b + EXTS(DS || 0b00)
 331     RT <- EXTS(MEM(EA, 4))
 332
 333 Special Registers Altered:
 334
 335     None
 336
 337 # Load Word Algebraic Indexed
 338
 339 X-Form
 340
 341 * lwax RT,RA,RB
 342
 343 Pseudo-code:
 344
 345     b <- (RA|0)
 346     EA <- b + (RB)
 347     RT <- EXTS(MEM(EA, 4))
 348
 349 Special Registers Altered:
 350
 351     None
 352
 353 # Load Word Algebraic with Update Indexed
 354
 355 X-Form
 356
 357 * lwaux RT,RA,RB
 358
 359 Pseudo-code:
 360
 361     EA <- (RA) + (RB)
 362     RT <- EXTS(MEM(EA, 4))
 363     RA <- EA
 364
 365 Special Registers Altered:
 366
 367     None
 368
 369 # Load Doubleword
 370
 371 DS-Form
 372
 373 * ld RT,DS(RA)
 374
 375 Pseudo-code:
 376
 377     b <- (RA|0)
 378     EA <- b + EXTS(DS || 0b00)
 379     RT <- MEM(EA, 8)
 380
 381 Special Registers Altered:
 382
 383     None
 384
 385 # Load Doubleword Indexed
 386
 387 X-Form
 388
 389 * ldx RT,RA,RB
 390
 391 Pseudo-code:
 392
 393     b <- (RA|0)
 394     EA <- b + (RB)
 395     RT <- MEM(EA, 8)
 396
 397 Special Registers Altered:
 398
 399     None
 400
 401 # Load Doubleword with Update Indexed
 402
 403 DS-Form
 404
 405 * ldu RT,DS(RA)
 406
 407 Pseudo-code:
 408
 409     EA <- (RA) + EXTS(DS || 0b00)
 410     RT <- MEM(EA, 8)
 411     RA <- EA
 412
 413 Special Registers Altered:
 414
 415     None
 416
 417 # Load Doubleword with Update Indexed
 418
 419 X-Form
 420
 421 * ldux RT,RA,RB
 422
 423 Pseudo-code:
 424
 425     EA <- (RA) + (RB)
 426     RT <- MEM(EA, 8)
 427     RA <- EA
 428
 429 Special Registers Altered:
 430
 431     None
 432
 433 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
 434
 435 <!-- The contents of register RS are stored into the byte, halfword, word, or -->
 436 <!-- doubleword in storage addressed by EA. -->
 437
 438 <!-- Many of the Store instructions have an “update” form, in which register RA is -->
 439 <!-- updated with the effective address. For these forms, the following rules apply. -->
 440
 441 <!-- If RA!=0, the effective address is placed into register RA. -->
 442
 443 <!-- If RS=RA, the contents of register RS are copied to the target storage element -->
 444 <!-- and then EA is placed into RA (RS). -->
 445
 446 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
 447
 448 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
 449
 450 <!-- For lq, the quadword in storage addressed by EA is loaded into an even-odd pair -->
 451 <!-- of GPRs as follows. In Big-Endian mode, the even-numbered GPR is loaded with -->
 452 <!-- the doubleword from storage addressed by EA and the odd-numbered GPR is loaded -->
 453 <!-- with the doubleword addressed by EA+8. In Little-Endian mode, the even-numbered -->
 454 <!-- GPR is loaded with the byte-reversed doubleword from storage addressed by EA+8 -->
 455 <!-- and the odd-numbered GPR is loaded with the byte-reversed doubleword addressed -->
 456 <!-- by EA. -->
 457
 458 # Load Quadword
 459
 460 DQ-Form
 461
 462 * lq RTp,DQ(RA)
 463
 464 Pseudo-code:
 465
 466     b <- (RA|0)
 467     EA <- b + EXTS(DQ || 0b0000)
 468     RTp <- MEM(EA, 16)
 469
 470 Special Registers Altered:
 471
 472     None
 473
 474 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
 475
 476 # Load Halfword Byte-Reverse Indexed
 477
 478 X-Form
 479
 480 * lhbrx RT,RA,RB
 481
 482 Pseudo-code:
 483
 484     b <- (RA|0)
 485     EA <- b + (RB)
 486     load_data <- MEM(EA, 2)
 487     RT <- [0]*48 || load_data[8:15] || load_data[0:7]
 488
 489 Special Registers Altered:
 490
 491     None
 492
 493 # Load Word Byte-Reverse Indexed
 494
 495 X-Form
 496
 497 * lwbrx RT,RA,RB
 498
 499 Pseudo-code:
 500
 501     b <- (RA|0)
 502     EA <- b + (RB)
 503     load_data <- MEM(EA, 4)
 504     RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
 505                     || load_data[8:15]  || load_data[0:7])
 506
 507 Special Registers Altered:
 508
 509     None
 510
 511
 512 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
 513
 514 # Load Doubleword Byte-Reverse Indexed
 515
 516 X-Form
 517
 518 * ldbrx RT,RA,RB
 519
 520 Pseudo-code:
 521
 522     b <- (RA|0)
 523     EA <- b + (RB)
 524     load_data <- MEM(EA, 8)
 525     RT <- (load_data[56:63] || load_data[48:55]
 526         || load_data[40:47] || load_data[32:39]
 527         || load_data[24:31] || load_data[16:23]
 528         || load_data[8:15]  || load_data[0:7])
 529
 530 Special Registers Altered:
 531
 532     None
 533
 534 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
 535
 536 # Load Multiple Word
 537
 538 DQ-Form
 539
 540 * lmw RT,D(RA)
 541
 542 Pseudo-code:
 543
 544     b <- (RA|0)
 545     EA <- b + EXTS(D)
 546     r <- RT[0:63]
 547     do while r <=  31
 548         GPR(r) <- [0]*32 || MEM(EA, 4)
 549         r <- r + 1
 550         EA <- EA + 4
 551
 552 Special Registers Altered:
 553
 554     None
 555