1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
3 <!-- This defines instructions that load from RAM to a register -->
5 <!-- Note that these pages also define equivalent store instructions, -->
6 <!-- these are described in fixedstore.mdwn -->
8 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
9 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
10 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
11 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
12 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
13 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
14 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
18 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
20 <!-- The byte, halfword, word, or doubleword in storage addressed by EA is loaded -->
21 <!-- into register RT. -->
23 <!-- Many of the Load instructions have an “update” form, in which register RA is -->
24 <!-- updated with the effective address. For these forms, if RA!=0 and RA!=RT, the -->
25 <!-- effective address is placed into register RA and the storage element (byte, -->
26 <!-- halfword, word, or doubleword) addressed by EA is loaded into RT. -->
39 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
41 Special Registers Altered:
45 # Load Byte and Zero Indexed
55 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
57 Special Registers Altered:
61 # Load Byte and Zero with Update
70 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
73 Special Registers Altered:
77 # Load Byte and Zero with Update Indexed
86 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
89 Special Registers Altered:
93 # Load Halfword and Zero
103 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
105 Special Registers Altered:
109 # Load Halfword and Zero Indexed
119 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
121 Special Registers Altered:
125 # Load Halfword and Zero with Update
134 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
137 Special Registers Altered:
141 # Load Halfword and Zero with Update Indexed
150 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
153 Special Registers Altered:
157 # Load Halfword Algebraic
167 RT <- EXTS(MEM(EA, 2))
169 Special Registers Altered:
173 # Load Halfword Algebraic Indexed
183 RT <- EXTS(MEM(EA, 2))
185 Special Registers Altered:
189 # Load Halfword Algebraic with Update
198 RT <- EXTS(MEM(EA, 2))
201 Special Registers Altered:
205 # Load Halfword Algebraic with Update Indexed
214 RT <- EXTS(MEM(EA, 2))
217 Special Registers Altered:
231 RT <- [0] * 32 || MEM(EA, 4)
233 Special Registers Altered:
237 # Load Word and Zero Indexed
247 RT <- [0] * 32 || MEM(EA, 4)
249 Special Registers Altered:
253 # Load Word and Zero with Update
262 RT <- [0]*32 || MEM(EA, 4)
265 Special Registers Altered:
269 # Load Word and Zero with Update Indexed
278 RT <- [0] * 32 || MEM(EA, 4)
281 Special Registers Altered:
285 # Load Word Algebraic
294 EA <- b + EXTS(DS || 0b00)
295 RT <- EXTS(MEM(EA, 4))
297 Special Registers Altered:
301 # Load Word Algebraic Indexed
311 RT <- EXTS(MEM(EA, 4))
313 Special Registers Altered:
317 # Load Word Algebraic with Update Indexed
326 RT <- EXTS(MEM(EA, 4))
329 Special Registers Altered:
342 EA <- b + EXTS(DS || 0b00)
345 Special Registers Altered:
349 # Load Doubleword Indexed
361 Special Registers Altered:
365 # Load Doubleword with Update Indexed
373 EA <- (RA) + EXTS(DS || 0b00)
377 Special Registers Altered:
381 # Load Doubleword with Update Indexed
393 Special Registers Altered:
397 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
399 <!-- The contents of register RS are stored into the byte, halfword, word, or -->
400 <!-- doubleword in storage addressed by EA. -->
402 <!-- Many of the Store instructions have an “update” form, in which register RA is -->
403 <!-- updated with the effective address. For these forms, the following rules apply. -->
405 <!-- If RA!=0, the effective address is placed into register RA. -->
407 <!-- If RS=RA, the contents of register RS are copied to the target storage element -->
408 <!-- and then EA is placed into RA (RS). -->
410 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
412 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
414 <!-- For lq, the quadword in storage addressed by EA is loaded into an even-odd pair -->
415 <!-- of GPRs as follows. In Big-Endian mode, the even-numbered GPR is loaded with -->
416 <!-- the doubleword from storage addressed by EA and the odd-numbered GPR is loaded -->
417 <!-- with the doubleword addressed by EA+8. In Little-Endian mode, the even-numbered -->
418 <!-- GPR is loaded with the byte-reversed doubleword from storage addressed by EA+8 -->
419 <!-- and the odd-numbered GPR is loaded with the byte-reversed doubleword addressed -->
431 EA <- b + EXTS(DQ || 0b0000)
434 Special Registers Altered:
438 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
440 # Load Halfword Byte-Reverse Indexed
450 load_data <- MEM(EA, 2)
451 RT <- [0]*48 || load_data[8:15] || load_data[0:7]
453 Special Registers Altered:
457 # Load Word Byte-Reverse Indexed
467 load_data <- MEM(EA, 4)
468 RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
469 || load_data[8:15] || load_data[0:7])
471 Special Registers Altered:
476 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
478 # Load Doubleword Byte-Reverse Indexed
488 load_data <- MEM(EA, 8)
489 RT <- (load_data[56:63] || load_data[48:55]
490 || load_data[40:47] || load_data[32:39]
491 || load_data[24:31] || load_data[16:23]
492 || load_data[8:15] || load_data[0:7])
494 Special Registers Altered:
498 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
512 GPR(r) <- [0]*32 || MEM(EA, 4)
516 Special Registers Altered: