openpower/isa/fixedload.mdwn

   1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
   2
   3 <!-- This defines instructions that load from RAM to a register -->
   4
   5 <!-- Note that these pages also define equivalent store instructions, -->
   6 <!-- these are described in fixedstore.mdwn -->
   7
   8 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
   9 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
  10 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
  11 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
  12 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
  13 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
  14 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
  15
  16
  17
  18 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
  19
  20 <!-- The byte, halfword, word, or doubleword in storage addressed by EA is loaded -->
  21 <!-- into register RT. -->
  22
  23 <!-- Many of the Load instructions have an “update” form, in which register RA is -->
  24 <!-- updated with the effective address. For these forms, if RA!=0 and RA!=RT, the -->
  25 <!-- effective address is placed into register RA and the storage element (byte, -->
  26 <!-- halfword, word, or doubleword) addressed by EA is loaded into RT. -->
  27
  28
  29 # Load Byte and Zero
  30
  31 D-Form
  32
  33 * lbz RT,D(RA)
  34
  35 Pseudo-code:
  36
  37     b <- (RA|0)
  38     EA <- b + EXTS(D)
  39     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  40
  41 Description:
  42
  43     Let the effective address (EA) be the sum (RA|0)+ D.
  44
  45     The byte in storage addressed by EA is loaded into RT[56:63].
  46     RT[0:55] are set to 0.
  47
  48 Special Registers Altered:
  49
  50     None
  51
  52 # Load Byte and Zero Indexed
  53
  54 X-Form
  55
  56 * lbzx RT,RA,RB
  57
  58 Pseudo-code:
  59
  60     b <- (RA|0)
  61     EA <- b + (RB)
  62     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  63
  64 Description:
  65
  66     Let the effective address (EA) be the sum (RA|0)+ (RB).
  67
  68     The byte in storage addressed by EA is loaded into RT[56:63].
  69     RT[0:55] are set to 0.
  70
  71 Special Registers Altered:
  72
  73     None
  74
  75 # Load Byte and Zero with Update
  76
  77 D-Form
  78
  79 * lbzu RT,D(RA)
  80
  81 Pseudo-code:
  82
  83     EA <- (RA) + EXTS(D)
  84     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  85     RA <- EA
  86
  87 Description:
  88
  89     Let the effective address (EA) be the sum (RA)+ D.
  90
  91     The byte in storage addressed by EA is loaded into RT[56:63].
  92     RT[0:55] are set to 0.
  93
  94     EA is placed into register RA.
  95
  96     If RA=0 or RA=RT, the instruction form is invalid.
  97
  98 Special Registers Altered:
  99
 100     None
 101
 102 # Load Byte and Zero with Update Indexed
 103
 104 X-Form
 105
 106 * lbzux RT,RA,RB
 107
 108 Pseudo-code:
 109
 110     EA <- (RA) + (RB)
 111     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
 112     RA <- EA
 113
 114 Description:
 115
 116     Let the effective address (EA) be the sum (RA)+ (RB).
 117
 118     The byte in storage addressed by EA is loaded into RT[56:63].
 119     RT[0:55] are set to 0.
 120
 121     EA is placed into register RA.
 122
 123     If RA=0 or RA=RT, the instruction form is invalid.
 124
 125 Special Registers Altered:
 126
 127     None
 128
 129 # Load Halfword and Zero
 130
 131 D-Form
 132
 133 * lhz RT,D(RA)
 134
 135 Pseudo-code:
 136
 137     b <- (RA|0)
 138     EA <- b + EXTS(D)
 139     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 140
 141 Description:
 142
 143     Let the effective address (EA) be the sum (RA|0)+ D.
 144
 145     The halfword in storage addressed by EA is loaded into RT[48:63].
 146     RT[0:47] are set to 0.
 147
 148 Special Registers Altered:
 149
 150     None
 151
 152 # Load Halfword and Zero Indexed
 153
 154 X-Form
 155
 156 * lhzx RT,RA,RB
 157
 158 Pseudo-code:
 159
 160     b <- (RA|0)
 161     EA <- b + (RB)
 162     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 163
 164 Description:
 165
 166     Let the effective address (EA) be the sum (RA|0)+ (RB).
 167
 168     The halfword in storage addressed by EA is loaded into RT[48:63].
 169     RT[0:47] are set to 0.
 170
 171 Special Registers Altered:
 172
 173     None
 174
 175 # Load Halfword and Zero with Update
 176
 177 D-Form
 178
 179 * lhzu RT,D(RA)
 180
 181 Pseudo-code:
 182
 183     EA <- (RA) + EXTS(D)
 184     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 185     RA <- EA
 186
 187 Description:
 188
 189     Let the effective address (EA) be the sum (RA)+ D.
 190
 191     The halfword in storage addressed by EA is loaded into RT[48:63].
 192     RT[0:47] are set to 0.
 193
 194     EA is placed into register RA.
 195
 196     If RA=0 or RA=RT, the instruction form is invalid.
 197
 198 Special Registers Altered:
 199
 200     None
 201
 202 # Load Halfword and Zero with Update Indexed
 203
 204 X-Form
 205
 206 * lhzux RT,RA,RB
 207
 208 Pseudo-code:
 209
 210     EA <- (RA) + (RB)
 211     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 212     RA <- EA
 213
 214 Description:
 215
 216     Let the effective address (EA) be the sum (RA)+ (RB).
 217
 218     The halfword in storage addressed by EA is loaded into RT[48:63].
 219     RT[0:47] are set to 0.
 220
 221     EA is placed into register RA.
 222
 223     If RA=0 or RA=RT, the instruction form is invalid.
 224
 225 Special Registers Altered:
 226
 227     None
 228
 229 # Load Halfword Algebraic
 230
 231 D-Form
 232
 233 * lha RT,D(RA)
 234
 235 Pseudo-code:
 236
 237     b <- (RA|0)
 238     EA <- b + EXTS(D)
 239     RT <- EXTS(MEM(EA, 2))
 240
 241 Description:
 242
 243     Let the effective address (EA) be the sum (RA|0)+ D.
 244
 245     The halfword in storage addressed by EA is loaded into RT[48:63].
 246     RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
 247
 248 Special Registers Altered:
 249
 250     None
 251
 252 # Load Halfword Algebraic Indexed
 253
 254 X-Form
 255
 256 * lhax RT,RA,RB
 257
 258 Pseudo-code:
 259
 260     b <- (RA|0)
 261     EA <- b + (RB)
 262     RT <- EXTS(MEM(EA, 2))
 263
 264 Description:
 265
 266     Let the effective address (EA) be the sum (RA|0)+ (RB).
 267
 268     The halfword in storage addressed by EA is loaded into RT[48:63].
 269     RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
 270
 271 Special Registers Altered:
 272
 273     None
 274
 275 # Load Halfword Algebraic with Update
 276
 277 D-Form
 278
 279 * lhau RT,D(RA)
 280
 281 Pseudo-code:
 282
 283     EA <- (RA) + EXTS(D)
 284     RT <- EXTS(MEM(EA, 2))
 285     RA <- EA
 286
 287 Description:
 288
 289     Let the effective address (EA) be the sum (RA)+ D.
 290     The halfword in storage addressed by EA is loaded into RT[48:63].
 291     RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
 292
 293     EA is placed into register RA.
 294
 295     If RA=0 or RA=RT, the instruction form is invalid.
 296
 297 Special Registers Altered:
 298
 299     None
 300
 301 # Load Halfword Algebraic with Update Indexed
 302
 303 X-Form
 304
 305 * lhaux RT,RA,RB
 306
 307 Pseudo-code:
 308
 309     EA <- (RA) + (RB)
 310     RT <- EXTS(MEM(EA, 2))
 311     RA <- EA
 312
 313 Description:
 314
 315     Let the effective address (EA) be the sum (RA)+ (RB).
 316
 317     The halfword in storage addressed by EA is loaded into RT[48:63].
 318     RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
 319
 320     EA is placed into register RA.
 321
 322     If RA=0 or RA=RT, the instruction form is invalid.
 323
 324 Special Registers Altered:
 325
 326     None
 327
 328 # Load Word and Zero
 329
 330 D-Form
 331
 332 * lwz RT,D(RA)
 333
 334 Pseudo-code:
 335
 336     b <- (RA|0)
 337     EA <- b + EXTS(D)
 338     RT <- [0] * 32 || MEM(EA, 4)
 339
 340 Description:
 341
 342     Let the effective address (EA) be the sum (RA|0)+ D.
 343
 344     The word in storage addressed by EA is loaded into RT[32:63].
 345     RT[0:31] are set to 0.
 346
 347 Special Registers Altered:
 348
 349     None
 350
 351 # Load Word and Zero Indexed
 352
 353 X-Form
 354
 355 * lwzx RT,RA,RB
 356
 357 Pseudo-code:
 358
 359     b <- (RA|0)
 360     EA <- b + (RB)
 361     RT <- [0] * 32 || MEM(EA, 4)
 362
 363 Description:
 364
 365     Let the effective address (EA) be the sum (RA|0)+ (RB).
 366
 367     The word in storage addressed by EA is loaded into RT[32:63].
 368     RT[0:31] are set to 0.
 369
 370 Special Registers Altered:
 371
 372     None
 373
 374 # Load Word and Zero with Update
 375
 376 D-Form
 377
 378 * lwzu RT,D(RA)
 379
 380 Pseudo-code:
 381
 382     EA <- (RA) + EXTS(D)
 383     RT <- [0]*32 || MEM(EA, 4)
 384     RA <- EA
 385
 386 Description:
 387
 388     Let the effective address (EA) be the sum (RA)+ D.
 389
 390     The word in storage addressed by EA is loaded into RT[32:63].
 391     RT[0:31] are set to 0.
 392
 393     EA is placed into register RA.
 394
 395     If RA=0 or RA=RT, the instruction form is invalid.
 396
 397 Special Registers Altered:
 398
 399     None
 400
 401 # Load Word and Zero with Update Indexed
 402
 403 X-Form
 404
 405 * lwzux RT,RA,RB
 406
 407 Pseudo-code:
 408
 409     EA <- (RA) + (RB)
 410     RT <- [0] * 32 || MEM(EA, 4)
 411     RA <- EA
 412
 413 Description:
 414
 415     Let the effective address (EA) be the sum (RA)+ (RB).
 416
 417     The word in storage addressed by EA is loaded into RT[32:63].
 418     RT[0:31] are set to 0.
 419
 420     EA is placed into register RA.
 421
 422     If RA=0 or RA=RT, the instruction form is invalid.
 423
 424 Special Registers Altered:
 425
 426     None
 427
 428 # Load Word Algebraic
 429
 430 DS-Form
 431
 432 * lwa RT,DS(RA)
 433
 434 Pseudo-code:
 435
 436     b <- (RA|0)
 437     EA <- b + EXTS(DS || 0b00)
 438     RT <- EXTS(MEM(EA, 4))
 439
 440 Description:
 441
 442     Let the effective address (EA) be the sum (RA|0)+ (DS||0b00).
 443
 444     The word in storage addressed by EA is loaded into RT[32:63].
 445     RT[0:31] are filled with a copy of bit 0 of the loaded word.
 446
 447 Special Registers Altered:
 448
 449     None
 450
 451 # Load Word Algebraic Indexed
 452
 453 X-Form
 454
 455 * lwax RT,RA,RB
 456
 457 Pseudo-code:
 458
 459     b <- (RA|0)
 460     EA <- b + (RB)
 461     RT <- EXTS(MEM(EA, 4))
 462
 463 Description:
 464
 465     Let the effective address (EA) be the sum (RA|0)+ (RB).
 466
 467     The word in storage addressed by EA is loaded into RT[32:63].
 468     RT[0:31] are filled with a copy of bit 0 of the loaded word.
 469
 470 Special Registers Altered:
 471
 472     None
 473
 474 # Load Word Algebraic with Update Indexed
 475
 476 X-Form
 477
 478 * lwaux RT,RA,RB
 479
 480 Pseudo-code:
 481
 482     EA <- (RA) + (RB)
 483     RT <- EXTS(MEM(EA, 4))
 484     RA <- EA
 485
 486 Description:
 487
 488     Let the effective address (EA) be the sum (RA)+ (RB).
 489
 490     The word in storage addressed by EA is loaded into RT[32:63].
 491     RT[0:31] are filled with a copy of bit 0 of the loaded word.
 492
 493     EA is placed into register RA.
 494
 495     If RA=0 or RA=RT, the instruction form is invalid.
 496
 497 Special Registers Altered:
 498
 499     None
 500
 501 # Load Doubleword
 502
 503 DS-Form
 504
 505 * ld RT,DS(RA)
 506
 507 Pseudo-code:
 508
 509     b <- (RA|0)
 510     EA <- b + EXTS(DS || 0b00)
 511     RT <- MEM(EA, 8)
 512
 513 Description:
 514
 515     Let the effective address (EA) be the sum (RA|0)+ (DS||0b00).
 516
 517     The doubleword in storage addressed by EA is loaded into RT.
 518
 519 Special Registers Altered:
 520
 521     None
 522
 523 # Load Doubleword Indexed
 524
 525 X-Form
 526
 527 * ldx RT,RA,RB
 528
 529 Pseudo-code:
 530
 531     b <- (RA|0)
 532     EA <- b + (RB)
 533     RT <- MEM(EA, 8)
 534
 535 Description:
 536
 537     Let the effective address (EA) be the sum (RA|0)+ (RB).
 538
 539     The doubleword in storage addressed by EA is loaded into RT.
 540
 541 Special Registers Altered:
 542
 543     None
 544
 545 # Load Doubleword with Update Indexed
 546
 547 DS-Form
 548
 549 * ldu RT,DS(RA)
 550
 551 Pseudo-code:
 552
 553     EA <- (RA) + EXTS(DS || 0b00)
 554     RT <- MEM(EA, 8)
 555     RA <- EA
 556
 557 Description:
 558
 559     Let the effective address (EA) be the sum (RA)+ (DS||0b00).
 560
 561     The doubleword in storage addressed by EA is loaded into RT.
 562
 563     EA is placed into register RA.
 564
 565     If RA=0 or RA=RT, the instruction form is invalid.
 566
 567 Special Registers Altered:
 568
 569     None
 570
 571 # Load Doubleword with Update Indexed
 572
 573 X-Form
 574
 575 * ldux RT,RA,RB
 576
 577 Pseudo-code:
 578
 579     EA <- (RA) + (RB)
 580     RT <- MEM(EA, 8)
 581     RA <- EA
 582
 583 Description:
 584
 585     Let the effective address (EA) be the sum (RA)+ (RB).
 586
 587     The doubleword in storage addressed by EA is loaded into RT.
 588
 589     EA is placed into register RA.
 590
 591     If RA=0 or RA=RT, the instruction form is invalid.
 592
 593 Special Registers Altered:
 594
 595     None
 596
 597 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
 598
 599 <!-- The contents of register RS are stored into the byte, halfword, word, or -->
 600 <!-- doubleword in storage addressed by EA. -->
 601
 602 <!-- Many of the Store instructions have an “update” form, in which register RA is -->
 603 <!-- updated with the effective address. For these forms, the following rules apply. -->
 604
 605 <!-- If RA!=0, the effective address is placed into register RA. -->
 606
 607 <!-- If RS=RA, the contents of register RS are copied to the target storage element -->
 608 <!-- and then EA is placed into RA (RS). -->
 609
 610 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
 611
 612 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
 613
 614 <!-- For lq, the quadword in storage addressed by EA is loaded into an even-odd pair -->
 615 <!-- of GPRs as follows. In Big-Endian mode, the even-numbered GPR is loaded with -->
 616 <!-- the doubleword from storage addressed by EA and the odd-numbered GPR is loaded -->
 617 <!-- with the doubleword addressed by EA+8. In Little-Endian mode, the even-numbered -->
 618 <!-- GPR is loaded with the byte-reversed doubleword from storage addressed by EA+8 -->
 619 <!-- and the odd-numbered GPR is loaded with the byte-reversed doubleword addressed -->
 620 <!-- by EA. -->
 621
 622 # Load Quadword
 623
 624 DQ-Form
 625
 626 * lq RTp,DQ(RA)
 627
 628 Pseudo-code:
 629
 630     b <- (RA|0)
 631     EA <- b + EXTS(DQ || 0b0000)
 632     RTp <- MEM(EA, 16)
 633
 634 Description:
 635
 636     Let the effective address (EA) be the sum (RA|0)+ (DQ||0b0000).
 637     The quadword in storage addressed by EA is loaded into register pair RTp.
 638
 639     If RTp is odd or RTp=RA, the instruction form is invalid.
 640     If RTp=RA, an attempt to execute this instruction will
 641     invoke the system illegal instruction error handler. (The
 642     RTp=RA case includes the case of RTp=RA=0.)
 643
 644     The quadword in storage addressed by EA is loaded
 645     into an even-odd pair of GPRs as follows. In
 646     Big-Endian mode, the even-numbered GPR is loaded
 647     with the doubleword from storage addressed by EA
 648     and the odd-numbered GPR is loaded with the double-
 649     word addressed by EA+8. In Little-Endian mode, the
 650     even-numbered GPR is loaded with the byte-reversed
 651     doubleword from storage addressed by EA+8 and the
 652     odd-numbered GPR is loaded with the byte-reversed
 653     doubleword addressed by EA.
 654
 655 Special Registers Altered:
 656
 657     None
 658
 659 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
 660
 661 # Load Halfword Byte-Reverse Indexed
 662
 663 X-Form
 664
 665 * lhbrx RT,RA,RB
 666
 667 Pseudo-code:
 668
 669     b <- (RA|0)
 670     EA <- b + (RB)
 671     load_data <- MEM(EA, 2)
 672     RT <- [0]*48 || load_data[8:15] || load_data[0:7]
 673
 674 Description:
 675
 676     Let the effective address (EA) be the sum (RA|0)+(RB).
 677
 678     Bits 0:7 of the halfword in storage addressed by EA are
 679     loaded into RT[56:63]. Bits 8:15 of the halfword in storage
 680     addressed by EA are loaded into RT[48:55].
 681     RT[0:47] are set to 0.
 682
 683 Special Registers Altered:
 684
 685     None
 686
 687 # Load Word Byte-Reverse Indexed
 688
 689 X-Form
 690
 691 * lwbrx RT,RA,RB
 692
 693 Pseudo-code:
 694
 695     b <- (RA|0)
 696     EA <- b + (RB)
 697     load_data <- MEM(EA, 4)
 698     RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
 699                     || load_data[8:15]  || load_data[0:7])
 700
 701 Description:
 702
 703     Let the effective address (EA) be the sum (RA|0)+ (RB).
 704
 705     Bits 0:7 of the word in storage addressed
 706     by EA are loaded into RT[56:63]. Bits 8:15 of the word in
 707     storage addressed by EA are loaded into RT[48:55]. Bits
 708     16:23 of the word in storage addressed by EA are
 709     loaded into RT[40:47]. Bits 24:31 of the word in storage
 710     addressed by EA are loaded into RT 32:39.
 711     RT[0:31] are set to 0.
 712
 713 Special Registers Altered:
 714
 715     None
 716
 717
 718 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
 719
 720 # Load Doubleword Byte-Reverse Indexed
 721
 722 X-Form
 723
 724 * ldbrx RT,RA,RB
 725
 726 Pseudo-code:
 727
 728     b <- (RA|0)
 729     EA <- b + (RB)
 730     load_data <- MEM(EA, 8)
 731     RT <- (load_data[56:63] || load_data[48:55]
 732         || load_data[40:47] || load_data[32:39]
 733         || load_data[24:31] || load_data[16:23]
 734         || load_data[8:15]  || load_data[0:7])
 735
 736 Description:
 737
 738     Let the effective address (EA) be the sum (RA|0)+(RB).
 739
 740     Bits 0:7 of the doubleword in storage addressed by EA
 741     are loaded into RT[56:63]. Bits 8:15 of the doubleword in
 742     storage addressed by EA are loaded into RT[48:55]. Bits
 743     16:23 of the doubleword in storage addressed by EA
 744     are loaded into RT[40:47]. Bits 24:31 of the doubleword in
 745     storage addressed by EA are loaded into RT 32:39. Bits
 746     32:39 of the doubleword in storage addressed by EA
 747     are loaded into RT[24:31]. Bits 40:47 of the doubleword in
 748     storage addressed by EA are loaded into RT[16:23]. Bits
 749     48:55 of the doubleword in storage addressed by EA
 750     are loaded into RT[8:15]. Bits 56:63 of the doubleword in
 751     storage addressed by EA are loaded into RT[0:7].
 752
 753 Special Registers Altered:
 754
 755     None
 756
 757 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
 758
 759 # Load Multiple Word
 760
 761 D-Form
 762
 763 * lmw RT,D(RA)
 764
 765 Pseudo-code:
 766
 767     b <- (RA|0)
 768     EA <- b + EXTS(D)
 769     r <- RT[0:63]
 770     do while r <=  31
 771         GPR(r) <- [0]*32 || MEM(EA, 4)
 772         r <- r + 1
 773         EA <- EA + 4
 774
 775 Description:
 776
 777     Let n = (32-RT). Let the effective address (EA) be the
 778     sum (RA|0)+ D.
 779
 780     n consecutive words starting at EA are loaded into the
 781     low-order 32 bits of GPRs RT through 31. The
 782     high-order 32 bits of these GPRs are set to zero.
 783
 784     If RA is in the range of registers to be loaded, including
 785     the case in which RA=0, the instruction form is invalid.
 786
 787     This instruction is not supported in Little-Endian mode.
 788     If it is executed in Little-Endian mode, the system align-
 789     ment error handler is invoked.
 790
 791 Special Registers Altered:
 792
 793     None
 794