openpower/isa/fixedload.mdwn

   1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
   2
   3 <!-- This defines instructions that load from RAM to a register -->
   4
   5 <!-- Note that these pages also define equivalent store instructions, -->
   6 <!-- these are described in fixedstore.mdwn -->
   7
   8 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
   9 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
  10 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
  11 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
  12 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
  13 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
  14 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
  15
  16
  17
  18 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
  19
  20 <!-- The byte, halfword, word, or doubleword in storage addressed by EA is loaded -->
  21 <!-- into register RT. -->
  22
  23 <!-- Many of the Load instructions have an “update” form, in which register RA is -->
  24 <!-- updated with the effective address. For these forms, if RA!=0 and RA!=RT, the -->
  25 <!-- effective address is placed into register RA and the storage element (byte, -->
  26 <!-- halfword, word, or doubleword) addressed by EA is loaded into RT. -->
  27
  28
  29 # Load Byte and Zero
  30
  31 D-Form
  32
  33 * lbz RT,D(RA)
  34
  35 Pseudo-code:
  36
  37     b <- (RA|0)
  38     EA <- b + EXTS(D)
  39     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  40
  41 Description:
  42
  43     Let the effective address (EA) be the sum (RA|0)+ D.
  44     The byte in storage addressed by EA is loaded into
  45     RT[56:63]. RT[0:55] are set to 0.
  46
  47 Special Registers Altered:
  48
  49     None
  50
  51 # Load Byte and Zero Indexed
  52
  53 X-Form
  54
  55 * lbzx RT,RA,RB
  56
  57 Pseudo-code:
  58
  59     b <- (RA|0)
  60     EA <- b + (RB)
  61     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  62
  63 Description:
  64
  65     Let the effective address (EA) be the sum
  66     (RA|0)+ (RB). The byte in storage addressed by EA is
  67     loaded into RT[56:63] . RT[0:55] are set to 0.
  68
  69 Special Registers Altered:
  70
  71     None
  72
  73 # Load Byte and Zero with Update
  74
  75 D-Form
  76
  77 * lbzu RT,D(RA)
  78
  79 Pseudo-code:
  80
  81     EA <- (RA) + EXTS(D)
  82     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  83     RA <- EA
  84
  85 Description:
  86
  87     Let the effective address (EA) be the sum (RA)+ D. The
  88     byte in storage addressed by EA is loaded into RT[56:63].
  89     RT[0:55] are set to 0.
  90
  91     EA is placed into register RA.
  92
  93     If RA=0 or RA=RT, the instruction form is invalid.
  94
  95 Special Registers Altered:
  96
  97     None
  98
  99 # Load Byte and Zero with Update Indexed
 100
 101 X-Form
 102
 103 * lbzux RT,RA,RB
 104
 105 Pseudo-code:
 106
 107     EA <- (RA) + (RB)
 108     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
 109     RA <- EA
 110
 111 Description:
 112
 113     Let the effective address (EA) be the sum (RA)+ (RB).
 114     The byte in storage addressed by EA is loaded into
 115     RT[56:63]. RT[0:55] are set to 0.
 116
 117     EA is placed into register RA.
 118
 119     If RA=0 or RA=RT, the instruction form is invalid.
 120
 121 Special Registers Altered:
 122
 123     None
 124
 125 # Load Halfword and Zero
 126
 127 D-Form
 128
 129 * lhz RT,D(RA)
 130
 131 Pseudo-code:
 132
 133     b <- (RA|0)
 134     EA <- b + EXTS(D)
 135     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 136
 137 Description:
 138
 139     Let the effective address (EA) be the sum (RA|0)+ D.
 140     The halfword in storage addressed by EA is loaded into
 141     RT[48:63]. RT[0:47] are set to 0.
 142
 143 Special Registers Altered:
 144
 145     None
 146
 147 # Load Halfword and Zero Indexed
 148
 149 X-Form
 150
 151 * lhzx RT,RA,RB
 152
 153 Pseudo-code:
 154
 155     b <- (RA|0)
 156     EA <- b + (RB)
 157     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 158
 159 Description:
 160
 161     Let the effective address (EA) be the sum
 162     (RA|0)+ (RB). The halfword in storage addressed by
 163     EA is loaded into RT 48:63. RT 0:47 are set to 0.
 164
 165 Special Registers Altered:
 166
 167     None
 168
 169 # Load Halfword and Zero with Update
 170
 171 D-Form
 172
 173 * lhzu RT,D(RA)
 174
 175 Pseudo-code:
 176
 177     EA <- (RA) + EXTS(D)
 178     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 179     RA <- EA
 180
 181 Description:
 182
 183     Let the effective address (EA) be the sum (RA)+ D. The
 184     halfword in storage addressed by EA is loaded into
 185     RT[48:63]. RT[0:47] are set to 0.
 186
 187     EA is placed into register RA.
 188
 189     If RA=0 or RA=RT, the instruction form is invalid.
 190
 191 Special Registers Altered:
 192
 193     None
 194
 195 # Load Halfword and Zero with Update Indexed
 196
 197 X-Form
 198
 199 * lhzux RT,RA,RB
 200
 201 Pseudo-code:
 202
 203     EA <- (RA) + (RB)
 204     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 205     RA <- EA
 206
 207 Description:
 208
 209     Let the effective address (EA) be the sum (RA)+ (RB).
 210     The halfword in storage addressed by EA is loaded into
 211     RT[48:63]. RT[0:47] are set to 0.
 212
 213     EA is placed into register RA.
 214
 215     If RA=0 or RA=RT, the instruction form is invalid.
 216
 217 Special Registers Altered:
 218
 219     None
 220
 221 # Load Halfword Algebraic
 222
 223 D-Form
 224
 225 * lha RT,D(RA)
 226
 227 Pseudo-code:
 228
 229     b <- (RA|0)
 230     EA <- b + EXTS(D)
 231     RT <- EXTS(MEM(EA, 2))
 232
 233 Description:
 234
 235     Let the effective address (EA) be the sum (RA|0)+ D.
 236     The halfword in storage addressed by EA is loaded into
 237     RT48:63. RT 0:47 are filled with a copy of bit 0 of the
 238     loaded halfword.
 239
 240 Special Registers Altered:
 241
 242     None
 243
 244 # Load Halfword Algebraic Indexed
 245
 246 X-Form
 247
 248 * lhax RT,RA,RB
 249
 250 Pseudo-code:
 251
 252     b <- (RA|0)
 253     EA <- b + (RB)
 254     RT <- EXTS(MEM(EA, 2))
 255
 256 Special Registers Altered:
 257
 258     None
 259
 260 # Load Halfword Algebraic with Update
 261
 262 D-Form
 263
 264 * lhau RT,D(RA)
 265
 266 Pseudo-code:
 267
 268     EA <- (RA) + EXTS(D)
 269     RT <- EXTS(MEM(EA, 2))
 270     RA <- EA
 271
 272 Description:
 273
 274     Let the effective address (EA) be the sum (RA)+ D. The
 275     halfword in storage addressed by EA is loaded into
 276     RT[48:63]. RT[0:47] are filled with a copy of bit 0 of the
 277     loaded halfword.
 278
 279     EA is placed into register RA.
 280
 281     If RA=0 or RA=RT, the instruction form is invalid.
 282
 283 Special Registers Altered:
 284
 285     None
 286
 287 # Load Halfword Algebraic with Update Indexed
 288
 289 X-Form
 290
 291 * lhaux RT,RA,RB
 292
 293 Pseudo-code:
 294
 295     EA <- (RA) + (RB)
 296     RT <- EXTS(MEM(EA, 2))
 297     RA <- EA
 298
 299 Description:
 300
 301     Let the effective address (EA) be the sum (RA)+ (RB).
 302     The halfword in storage addressed by EA is loaded into
 303     RT48:63. RT 0:47 are filled with a copy of bit 0 of the
 304     loaded halfword.
 305
 306     EA is placed into register RA.
 307
 308     If RA=0 or RA=RT, the instruction form is invalid.
 309
 310 Special Registers Altered:
 311
 312     None
 313
 314 # Load Word and Zero
 315
 316 D-Form
 317
 318 * lwz RT,D(RA)
 319
 320 Pseudo-code:
 321
 322     b <- (RA|0)
 323     EA <- b + EXTS(D)
 324     RT <- [0] * 32 || MEM(EA, 4)
 325
 326 Special Registers Altered:
 327
 328     None
 329
 330 # Load Word and Zero Indexed
 331
 332 X-Form
 333
 334 * lwzx RT,RA,RB
 335
 336 Pseudo-code:
 337
 338     b <- (RA|0)
 339     EA <- b + (RB)
 340     RT <- [0] * 32 || MEM(EA, 4)
 341
 342 Special Registers Altered:
 343
 344     None
 345
 346 # Load Word and Zero with Update
 347
 348 D-Form
 349
 350 * lwzu RT,D(RA)
 351
 352 Pseudo-code:
 353
 354     EA <- (RA) + EXTS(D)
 355     RT <- [0]*32 || MEM(EA, 4)
 356     RA <- EA
 357
 358 Special Registers Altered:
 359
 360     None
 361
 362 # Load Word and Zero with Update Indexed
 363
 364 X-Form
 365
 366 * lwzux RT,RA,RB
 367
 368 Pseudo-code:
 369
 370     EA <- (RA) + (RB)
 371     RT <- [0] * 32 || MEM(EA, 4)
 372     RA <- EA
 373
 374 Special Registers Altered:
 375
 376     None
 377
 378 # Load Word Algebraic
 379
 380 DS-Form
 381
 382 * lwa RT,DS(RA)
 383
 384 Pseudo-code:
 385
 386     b <- (RA|0)
 387     EA <- b + EXTS(DS || 0b00)
 388     RT <- EXTS(MEM(EA, 4))
 389
 390 Special Registers Altered:
 391
 392     None
 393
 394 # Load Word Algebraic Indexed
 395
 396 X-Form
 397
 398 * lwax RT,RA,RB
 399
 400 Pseudo-code:
 401
 402     b <- (RA|0)
 403     EA <- b + (RB)
 404     RT <- EXTS(MEM(EA, 4))
 405
 406 Special Registers Altered:
 407
 408     None
 409
 410 # Load Word Algebraic with Update Indexed
 411
 412 X-Form
 413
 414 * lwaux RT,RA,RB
 415
 416 Pseudo-code:
 417
 418     EA <- (RA) + (RB)
 419     RT <- EXTS(MEM(EA, 4))
 420     RA <- EA
 421
 422 Special Registers Altered:
 423
 424     None
 425
 426 # Load Doubleword
 427
 428 DS-Form
 429
 430 * ld RT,DS(RA)
 431
 432 Pseudo-code:
 433
 434     b <- (RA|0)
 435     EA <- b + EXTS(DS || 0b00)
 436     RT <- MEM(EA, 8)
 437
 438 Special Registers Altered:
 439
 440     None
 441
 442 # Load Doubleword Indexed
 443
 444 X-Form
 445
 446 * ldx RT,RA,RB
 447
 448 Pseudo-code:
 449
 450     b <- (RA|0)
 451     EA <- b + (RB)
 452     RT <- MEM(EA, 8)
 453
 454 Special Registers Altered:
 455
 456     None
 457
 458 # Load Doubleword with Update Indexed
 459
 460 DS-Form
 461
 462 * ldu RT,DS(RA)
 463
 464 Pseudo-code:
 465
 466     EA <- (RA) + EXTS(DS || 0b00)
 467     RT <- MEM(EA, 8)
 468     RA <- EA
 469
 470 Special Registers Altered:
 471
 472     None
 473
 474 # Load Doubleword with Update Indexed
 475
 476 X-Form
 477
 478 * ldux RT,RA,RB
 479
 480 Pseudo-code:
 481
 482     EA <- (RA) + (RB)
 483     RT <- MEM(EA, 8)
 484     RA <- EA
 485
 486 Special Registers Altered:
 487
 488     None
 489
 490 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
 491
 492 <!-- The contents of register RS are stored into the byte, halfword, word, or -->
 493 <!-- doubleword in storage addressed by EA. -->
 494
 495 <!-- Many of the Store instructions have an “update” form, in which register RA is -->
 496 <!-- updated with the effective address. For these forms, the following rules apply. -->
 497
 498 <!-- If RA!=0, the effective address is placed into register RA. -->
 499
 500 <!-- If RS=RA, the contents of register RS are copied to the target storage element -->
 501 <!-- and then EA is placed into RA (RS). -->
 502
 503 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
 504
 505 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
 506
 507 <!-- For lq, the quadword in storage addressed by EA is loaded into an even-odd pair -->
 508 <!-- of GPRs as follows. In Big-Endian mode, the even-numbered GPR is loaded with -->
 509 <!-- the doubleword from storage addressed by EA and the odd-numbered GPR is loaded -->
 510 <!-- with the doubleword addressed by EA+8. In Little-Endian mode, the even-numbered -->
 511 <!-- GPR is loaded with the byte-reversed doubleword from storage addressed by EA+8 -->
 512 <!-- and the odd-numbered GPR is loaded with the byte-reversed doubleword addressed -->
 513 <!-- by EA. -->
 514
 515 # Load Quadword
 516
 517 DQ-Form
 518
 519 * lq RTp,DQ(RA)
 520
 521 Pseudo-code:
 522
 523     b <- (RA|0)
 524     EA <- b + EXTS(DQ || 0b0000)
 525     RTp <- MEM(EA, 16)
 526
 527 Special Registers Altered:
 528
 529     None
 530
 531 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
 532
 533 # Load Halfword Byte-Reverse Indexed
 534
 535 X-Form
 536
 537 * lhbrx RT,RA,RB
 538
 539 Pseudo-code:
 540
 541     b <- (RA|0)
 542     EA <- b + (RB)
 543     load_data <- MEM(EA, 2)
 544     RT <- [0]*48 || load_data[8:15] || load_data[0:7]
 545
 546 Special Registers Altered:
 547
 548     None
 549
 550 # Load Word Byte-Reverse Indexed
 551
 552 X-Form
 553
 554 * lwbrx RT,RA,RB
 555
 556 Pseudo-code:
 557
 558     b <- (RA|0)
 559     EA <- b + (RB)
 560     load_data <- MEM(EA, 4)
 561     RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
 562                     || load_data[8:15]  || load_data[0:7])
 563
 564 Special Registers Altered:
 565
 566     None
 567
 568
 569 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
 570
 571 # Load Doubleword Byte-Reverse Indexed
 572
 573 X-Form
 574
 575 * ldbrx RT,RA,RB
 576
 577 Pseudo-code:
 578
 579     b <- (RA|0)
 580     EA <- b + (RB)
 581     load_data <- MEM(EA, 8)
 582     RT <- (load_data[56:63] || load_data[48:55]
 583         || load_data[40:47] || load_data[32:39]
 584         || load_data[24:31] || load_data[16:23]
 585         || load_data[8:15]  || load_data[0:7])
 586
 587 Special Registers Altered:
 588
 589     None
 590
 591 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
 592
 593 # Load Multiple Word
 594
 595 DQ-Form
 596
 597 * lmw RT,D(RA)
 598
 599 Pseudo-code:
 600
 601     b <- (RA|0)
 602     EA <- b + EXTS(D)
 603     r <- RT[0:63]
 604     do while r <=  31
 605         GPR(r) <- [0]*32 || MEM(EA, 4)
 606         r <- r + 1
 607         EA <- EA + 4
 608
 609 Special Registers Altered:
 610
 611     None
 612