openpower/isa/fixedload.mdwn

   1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
   2
   3 <!-- This defines instructions that load from RAM to a register -->
   4
   5 <!-- Note that these pages also define equivalent store instructions, -->
   6 <!-- these are described in fixedstore.mdwn -->
   7
   8 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
   9 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
  10 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
  11 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
  12 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
  13 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
  14 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
  15
  16
  17
  18 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
  19
  20 <!-- The byte, halfword, word, or doubleword in storage addressed by EA is loaded -->
  21 <!-- into register RT. -->
  22
  23 <!-- Many of the Load instructions have an “update” form, in which register RA is -->
  24 <!-- updated with the effective address. For these forms, if RA!=0 and RA!=RT, the -->
  25 <!-- effective address is placed into register RA and the storage element (byte, -->
  26 <!-- halfword, word, or doubleword) addressed by EA is loaded into RT. -->
  27
  28
  29 # Load Byte and Zero
  30
  31 D-Form
  32
  33 * lbz RT,D(RA)
  34
  35 Pseudo-code:
  36
  37     b <- (RA|0)
  38     EA <- b + EXTS(D)
  39     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  40
  41 Description:
  42
  43 Let the effective address (EA) be the sum (RA|0)+ D.
  44 The byte in storage addressed by EA is loaded into
  45 RT[56:63]. RT[0:55] are set to 0.
  46
  47 Special Registers Altered:
  48
  49     None
  50
  51 # Load Byte and Zero Indexed
  52
  53 X-Form
  54
  55 * lbzx RT,RA,RB
  56
  57 Pseudo-code:
  58
  59     b <- (RA|0)
  60     EA <- b + (RB)
  61     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  62
  63 Special Registers Altered:
  64
  65     None
  66
  67 # Load Byte and Zero with Update
  68
  69 D-Form
  70
  71 * lbzu RT,D(RA)
  72
  73 Pseudo-code:
  74
  75     EA <- (RA) + EXTS(D)
  76     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  77     RA <- EA
  78
  79 Description:Let the effective address (EA) be the sum (RA)+ D. The
  80 byte in storage addressed by EA is loaded into RT 56:63.
  81 RT0:55 are set to 0.
  82 EA is placed into register RA.
  83 If RA=0 or RA=RT, the instruction form is invalid.
  84
  85 Special Registers Altered:
  86
  87     None
  88
  89 # Load Byte and Zero with Update Indexed
  90
  91 X-Form
  92
  93 * lbzux RT,RA,RB
  94
  95 Pseudo-code:
  96
  97     EA <- (RA) + (RB)
  98     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  99     RA <- EA
 100
 101 Description:Let the effective address (EA) be the sum (RA)+ (RB).
 102 The byte in storage addressed by EA is loaded into
 103 RT56:63. RT0:55 are set to 0.
 104 EA is placed into register RA.
 105 If RA=0 or RA=RT, the instruction form is invalid.
 106
 107 Special Registers Altered:
 108
 109     None
 110
 111 # Load Halfword and Zero
 112
 113 D-Form
 114
 115 * lhz RT,D(RA)
 116
 117 Pseudo-code:
 118
 119     b <- (RA|0)
 120     EA <- b + EXTS(D)
 121     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 122
 123 Special Registers Altered:
 124
 125     None
 126
 127 # Load Halfword and Zero Indexed
 128
 129 X-Form
 130
 131 * lhzx RT,RA,RB
 132
 133 Pseudo-code:
 134
 135     b <- (RA|0)
 136     EA <- b + (RB)
 137     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 138
 139 Special Registers Altered:
 140
 141     None
 142
 143 # Load Halfword and Zero with Update
 144
 145 D-Form
 146
 147 * lhzu RT,D(RA)
 148
 149 Pseudo-code:
 150
 151     EA <- (RA) + EXTS(D)
 152     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 153     RA <- EA
 154
 155 Special Registers Altered:
 156
 157     None
 158
 159 # Load Halfword and Zero with Update Indexed
 160
 161 X-Form
 162
 163 * lhzux RT,RA,RB
 164
 165 Pseudo-code:
 166
 167     EA <- (RA) + (RB)
 168     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 169     RA <- EA
 170
 171 Special Registers Altered:
 172
 173     None
 174
 175 # Load Halfword Algebraic
 176
 177 D-Form
 178
 179 * lha RT,D(RA)
 180
 181 Pseudo-code:
 182
 183     b <- (RA|0)
 184     EA <- b + EXTS(D)
 185     RT <- EXTS(MEM(EA, 2))
 186
 187 Special Registers Altered:
 188
 189     None
 190
 191 # Load Halfword Algebraic Indexed
 192
 193 X-Form
 194
 195 * lhax RT,RA,RB
 196
 197 Pseudo-code:
 198
 199     b <- (RA|0)
 200     EA <- b + (RB)
 201     RT <- EXTS(MEM(EA, 2))
 202
 203 Special Registers Altered:
 204
 205     None
 206
 207 # Load Halfword Algebraic with Update
 208
 209 D-Form
 210
 211 * lhau RT,D(RA)
 212
 213 Pseudo-code:
 214
 215     EA <- (RA) + EXTS(D)
 216     RT <- EXTS(MEM(EA, 2))
 217     RA <- EA
 218
 219 Special Registers Altered:
 220
 221     None
 222
 223 # Load Halfword Algebraic with Update Indexed
 224
 225 X-Form
 226
 227 * lhaux RT,RA,RB
 228
 229 Pseudo-code:
 230
 231     EA <- (RA) + (RB)
 232     RT <- EXTS(MEM(EA, 2))
 233     RA <- EA
 234
 235 Special Registers Altered:
 236
 237     None
 238
 239 # Load Word and Zero
 240
 241 D-Form
 242
 243 * lwz RT,D(RA)
 244
 245 Pseudo-code:
 246
 247     b <- (RA|0)
 248     EA <- b + EXTS(D)
 249     RT <- [0] * 32 || MEM(EA, 4)
 250
 251 Special Registers Altered:
 252
 253     None
 254
 255 # Load Word and Zero Indexed
 256
 257 X-Form
 258
 259 * lwzx RT,RA,RB
 260
 261 Pseudo-code:
 262
 263     b <- (RA|0)
 264     EA <- b + (RB)
 265     RT <- [0] * 32 || MEM(EA, 4)
 266
 267 Special Registers Altered:
 268
 269     None
 270
 271 # Load Word and Zero with Update
 272
 273 D-Form
 274
 275 * lwzu RT,D(RA)
 276
 277 Pseudo-code:
 278
 279     EA <- (RA) + EXTS(D)
 280     RT <- [0]*32 || MEM(EA, 4)
 281     RA <- EA
 282
 283 Special Registers Altered:
 284
 285     None
 286
 287 # Load Word and Zero with Update Indexed
 288
 289 X-Form
 290
 291 * lwzux RT,RA,RB
 292
 293 Pseudo-code:
 294
 295     EA <- (RA) + (RB)
 296     RT <- [0] * 32 || MEM(EA, 4)
 297     RA <- EA
 298
 299 Special Registers Altered:
 300
 301     None
 302
 303 # Load Word Algebraic
 304
 305 DS-Form
 306
 307 * lwa RT,DS(RA)
 308
 309 Pseudo-code:
 310
 311     b <- (RA|0)
 312     EA <- b + EXTS(DS || 0b00)
 313     RT <- EXTS(MEM(EA, 4))
 314
 315 Special Registers Altered:
 316
 317     None
 318
 319 # Load Word Algebraic Indexed
 320
 321 X-Form
 322
 323 * lwax RT,RA,RB
 324
 325 Pseudo-code:
 326
 327     b <- (RA|0)
 328     EA <- b + (RB)
 329     RT <- EXTS(MEM(EA, 4))
 330
 331 Special Registers Altered:
 332
 333     None
 334
 335 # Load Word Algebraic with Update Indexed
 336
 337 X-Form
 338
 339 * lwaux RT,RA,RB
 340
 341 Pseudo-code:
 342
 343     EA <- (RA) + (RB)
 344     RT <- EXTS(MEM(EA, 4))
 345     RA <- EA
 346
 347 Special Registers Altered:
 348
 349     None
 350
 351 # Load Doubleword
 352
 353 DS-Form
 354
 355 * ld RT,DS(RA)
 356
 357 Pseudo-code:
 358
 359     b <- (RA|0)
 360     EA <- b + EXTS(DS || 0b00)
 361     RT <- MEM(EA, 8)
 362
 363 Special Registers Altered:
 364
 365     None
 366
 367 # Load Doubleword Indexed
 368
 369 X-Form
 370
 371 * ldx RT,RA,RB
 372
 373 Pseudo-code:
 374
 375     b <- (RA|0)
 376     EA <- b + (RB)
 377     RT <- MEM(EA, 8)
 378
 379 Special Registers Altered:
 380
 381     None
 382
 383 # Load Doubleword with Update Indexed
 384
 385 DS-Form
 386
 387 * ldu RT,DS(RA)
 388
 389 Pseudo-code:
 390
 391     EA <- (RA) + EXTS(DS || 0b00)
 392     RT <- MEM(EA, 8)
 393     RA <- EA
 394
 395 Special Registers Altered:
 396
 397     None
 398
 399 # Load Doubleword with Update Indexed
 400
 401 X-Form
 402
 403 * ldux RT,RA,RB
 404
 405 Pseudo-code:
 406
 407     EA <- (RA) + (RB)
 408     RT <- MEM(EA, 8)
 409     RA <- EA
 410
 411 Special Registers Altered:
 412
 413     None
 414
 415 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
 416
 417 <!-- The contents of register RS are stored into the byte, halfword, word, or -->
 418 <!-- doubleword in storage addressed by EA. -->
 419
 420 <!-- Many of the Store instructions have an “update” form, in which register RA is -->
 421 <!-- updated with the effective address. For these forms, the following rules apply. -->
 422
 423 <!-- If RA!=0, the effective address is placed into register RA. -->
 424
 425 <!-- If RS=RA, the contents of register RS are copied to the target storage element -->
 426 <!-- and then EA is placed into RA (RS). -->
 427
 428 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
 429
 430 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
 431
 432 <!-- For lq, the quadword in storage addressed by EA is loaded into an even-odd pair -->
 433 <!-- of GPRs as follows. In Big-Endian mode, the even-numbered GPR is loaded with -->
 434 <!-- the doubleword from storage addressed by EA and the odd-numbered GPR is loaded -->
 435 <!-- with the doubleword addressed by EA+8. In Little-Endian mode, the even-numbered -->
 436 <!-- GPR is loaded with the byte-reversed doubleword from storage addressed by EA+8 -->
 437 <!-- and the odd-numbered GPR is loaded with the byte-reversed doubleword addressed -->
 438 <!-- by EA. -->
 439
 440 # Load Quadword
 441
 442 DQ-Form
 443
 444 * lq RTp,DQ(RA)
 445
 446 Pseudo-code:
 447
 448     b <- (RA|0)
 449     EA <- b + EXTS(DQ || 0b0000)
 450     RTp <- MEM(EA, 16)
 451
 452 Special Registers Altered:
 453
 454     None
 455
 456 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
 457
 458 # Load Halfword Byte-Reverse Indexed
 459
 460 X-Form
 461
 462 * lhbrx RT,RA,RB
 463
 464 Pseudo-code:
 465
 466     b <- (RA|0)
 467     EA <- b + (RB)
 468     load_data <- MEM(EA, 2)
 469     RT <- [0]*48 || load_data[8:15] || load_data[0:7]
 470
 471 Special Registers Altered:
 472
 473     None
 474
 475 # Load Word Byte-Reverse Indexed
 476
 477 X-Form
 478
 479 * lwbrx RT,RA,RB
 480
 481 Pseudo-code:
 482
 483     b <- (RA|0)
 484     EA <- b + (RB)
 485     load_data <- MEM(EA, 4)
 486     RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
 487                     || load_data[8:15]  || load_data[0:7])
 488
 489 Special Registers Altered:
 490
 491     None
 492
 493
 494 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
 495
 496 # Load Doubleword Byte-Reverse Indexed
 497
 498 X-Form
 499
 500 * ldbrx RT,RA,RB
 501
 502 Pseudo-code:
 503
 504     b <- (RA|0)
 505     EA <- b + (RB)
 506     load_data <- MEM(EA, 8)
 507     RT <- (load_data[56:63] || load_data[48:55]
 508         || load_data[40:47] || load_data[32:39]
 509         || load_data[24:31] || load_data[16:23]
 510         || load_data[8:15]  || load_data[0:7])
 511
 512 Special Registers Altered:
 513
 514     None
 515
 516 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
 517
 518 # Load Multiple Word
 519
 520 DQ-Form
 521
 522 * lmw RT,D(RA)
 523
 524 Pseudo-code:
 525
 526     b <- (RA|0)
 527     EA <- b + EXTS(D)
 528     r <- RT[0:63]
 529     do while r <=  31
 530         GPR(r) <- [0]*32 || MEM(EA, 4)
 531         r <- r + 1
 532         EA <- EA + 4
 533
 534 Special Registers Altered:
 535
 536     None
 537