1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
3 <!-- This defines instructions that load from RAM to a register -->
5 <!-- Note that these pages also define equivalent store instructions, -->
6 <!-- these are described in fixedstore.mdwn -->
8 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
9 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
10 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
11 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
12 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
13 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
14 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
18 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
20 <!-- The byte, halfword, word, or doubleword in storage addressed by EA is loaded -->
21 <!-- into register RT. -->
23 <!-- Many of the Load instructions have an “update” form, in which register RA is -->
24 <!-- updated with the effective address. For these forms, if RA!=0 and RA!=RT, the -->
25 <!-- effective address is placed into register RA and the storage element (byte, -->
26 <!-- halfword, word, or doubleword) addressed by EA is loaded into RT. -->
39 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
43 Let the effective address (EA) be the sum (RA|0)+ D.
44 The byte in storage addressed by EA is loaded into
45 RT[56:63]. RT[0:55] are set to 0.
47 Special Registers Altered:
51 # Load Byte and Zero Indexed
61 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
65 Let the effective address (EA) be the sum
66 (RA|0)+ (RB). The byte in storage addressed by EA is
67 loaded into RT[56:63] . RT[0:55] are set to 0.
69 Special Registers Altered:
73 # Load Byte and Zero with Update
82 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
87 Let the effective address (EA) be the sum (RA)+ D. The
88 byte in storage addressed by EA is loaded into RT[56:63].
89 RT[0:55] are set to 0.
91 EA is placed into register RA.
93 If RA=0 or RA=RT, the instruction form is invalid.
95 Special Registers Altered:
99 # Load Byte and Zero with Update Indexed
108 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
113 Let the effective address (EA) be the sum (RA)+ (RB).
114 The byte in storage addressed by EA is loaded into
115 RT[56:63]. RT[0:55] are set to 0.
117 EA is placed into register RA.
119 If RA=0 or RA=RT, the instruction form is invalid.
121 Special Registers Altered:
125 # Load Halfword and Zero
135 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
139 Let the effective address (EA) be the sum (RA|0)+ D.
140 The halfword in storage addressed by EA is loaded into
141 RT[48:63]. RT[0:47] are set to 0.
143 Special Registers Altered:
147 # Load Halfword and Zero Indexed
157 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
161 Let the effective address (EA) be the sum
162 (RA|0)+ (RB). The halfword in storage addressed by
163 EA is loaded into RT 48:63. RT 0:47 are set to 0.
165 Special Registers Altered:
169 # Load Halfword and Zero with Update
178 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
183 Let the effective address (EA) be the sum (RA)+ D. The
184 halfword in storage addressed by EA is loaded into
185 RT[48:63]. RT[0:47] are set to 0.
187 EA is placed into register RA.
189 If RA=0 or RA=RT, the instruction form is invalid.
191 Special Registers Altered:
195 # Load Halfword and Zero with Update Indexed
204 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
209 Let the effective address (EA) be the sum (RA)+ (RB).
210 The halfword in storage addressed by EA is loaded into
211 RT[48:63]. RT[0:47] are set to 0.
213 EA is placed into register RA.
215 If RA=0 or RA=RT, the instruction form is invalid.
217 Special Registers Altered:
221 # Load Halfword Algebraic
231 RT <- EXTS(MEM(EA, 2))
235 Let the effective address (EA) be the sum (RA|0)+ D.
236 The halfword in storage addressed by EA is loaded into
237 RT[48:63]. RT[0:47] are filled with a copy of bit 0 of the
240 Special Registers Altered:
244 # Load Halfword Algebraic Indexed
254 RT <- EXTS(MEM(EA, 2))
256 Special Registers Altered:
260 # Load Halfword Algebraic with Update
269 RT <- EXTS(MEM(EA, 2))
274 Let the effective address (EA) be the sum (RA)+ D. The
275 halfword in storage addressed by EA is loaded into
276 RT[48:63]. RT[0:47] are filled with a copy of bit 0 of the
279 EA is placed into register RA.
281 If RA=0 or RA=RT, the instruction form is invalid.
283 Special Registers Altered:
287 # Load Halfword Algebraic with Update Indexed
296 RT <- EXTS(MEM(EA, 2))
301 Let the effective address (EA) be the sum (RA)+ (RB).
302 The halfword in storage addressed by EA is loaded into
303 RT48:63. RT 0:47 are filled with a copy of bit 0 of the
306 EA is placed into register RA.
308 If RA=0 or RA=RT, the instruction form is invalid.
310 Special Registers Altered:
324 RT <- [0] * 32 || MEM(EA, 4)
326 Special Registers Altered:
330 # Load Word and Zero Indexed
340 RT <- [0] * 32 || MEM(EA, 4)
342 Special Registers Altered:
346 # Load Word and Zero with Update
355 RT <- [0]*32 || MEM(EA, 4)
358 Special Registers Altered:
362 # Load Word and Zero with Update Indexed
371 RT <- [0] * 32 || MEM(EA, 4)
374 Special Registers Altered:
378 # Load Word Algebraic
387 EA <- b + EXTS(DS || 0b00)
388 RT <- EXTS(MEM(EA, 4))
390 Special Registers Altered:
394 # Load Word Algebraic Indexed
404 RT <- EXTS(MEM(EA, 4))
406 Special Registers Altered:
410 # Load Word Algebraic with Update Indexed
419 RT <- EXTS(MEM(EA, 4))
422 Special Registers Altered:
435 EA <- b + EXTS(DS || 0b00)
438 Special Registers Altered:
442 # Load Doubleword Indexed
454 Special Registers Altered:
458 # Load Doubleword with Update Indexed
466 EA <- (RA) + EXTS(DS || 0b00)
470 Special Registers Altered:
474 # Load Doubleword with Update Indexed
486 Special Registers Altered:
490 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
492 <!-- The contents of register RS are stored into the byte, halfword, word, or -->
493 <!-- doubleword in storage addressed by EA. -->
495 <!-- Many of the Store instructions have an “update” form, in which register RA is -->
496 <!-- updated with the effective address. For these forms, the following rules apply. -->
498 <!-- If RA!=0, the effective address is placed into register RA. -->
500 <!-- If RS=RA, the contents of register RS are copied to the target storage element -->
501 <!-- and then EA is placed into RA (RS). -->
503 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
505 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
507 <!-- For lq, the quadword in storage addressed by EA is loaded into an even-odd pair -->
508 <!-- of GPRs as follows. In Big-Endian mode, the even-numbered GPR is loaded with -->
509 <!-- the doubleword from storage addressed by EA and the odd-numbered GPR is loaded -->
510 <!-- with the doubleword addressed by EA+8. In Little-Endian mode, the even-numbered -->
511 <!-- GPR is loaded with the byte-reversed doubleword from storage addressed by EA+8 -->
512 <!-- and the odd-numbered GPR is loaded with the byte-reversed doubleword addressed -->
524 EA <- b + EXTS(DQ || 0b0000)
527 Special Registers Altered:
531 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
533 # Load Halfword Byte-Reverse Indexed
543 load_data <- MEM(EA, 2)
544 RT <- [0]*48 || load_data[8:15] || load_data[0:7]
546 Special Registers Altered:
550 # Load Word Byte-Reverse Indexed
560 load_data <- MEM(EA, 4)
561 RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
562 || load_data[8:15] || load_data[0:7])
564 Special Registers Altered:
569 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
571 # Load Doubleword Byte-Reverse Indexed
581 load_data <- MEM(EA, 8)
582 RT <- (load_data[56:63] || load_data[48:55]
583 || load_data[40:47] || load_data[32:39]
584 || load_data[24:31] || load_data[16:23]
585 || load_data[8:15] || load_data[0:7])
587 Special Registers Altered:
591 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
605 GPR(r) <- [0]*32 || MEM(EA, 4)
609 Special Registers Altered: