openpower/isa/fixedload.mdwn

   1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
   2
   3 <!-- This defines instructions that load from RAM to a register -->
   4
   5 <!-- Note that these pages also define equivalent store instructions, -->
   6 <!-- these are described in fixedstore.mdwn -->
   7
   8 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
   9 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
  10 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
  11 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
  12 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
  13 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
  14 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
  15
  16
  17
  18 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
  19
  20 <!-- The byte, halfword, word, or doubleword in storage addressed by EA is loaded -->
  21 <!-- into register RT. -->
  22
  23 <!-- Many of the Load instructions have an “update” form, in which register RA is -->
  24 <!-- updated with the effective address. For these forms, if RA!=0 and RA!=RT, the -->
  25 <!-- effective address is placed into register RA and the storage element (byte, -->
  26 <!-- halfword, word, or doubleword) addressed by EA is loaded into RT. -->
  27
  28
  29 # Load Byte and Zero
  30
  31 D-Form
  32
  33 * lbz RT,D(RA)
  34
  35 Pseudo-code:
  36
  37     b <- (RA|0)
  38     EA <- b + EXTS(D)
  39     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  40
  41 Description:
  42
  43     Let the effective address (EA) be the sum (RA|0)+ D.
  44     The byte in storage addressed by EA is loaded into
  45     RT[56:63]. RT[0:55] are set to 0.
  46
  47 Special Registers Altered:
  48
  49     None
  50
  51 # Load Byte and Zero Indexed
  52
  53 X-Form
  54
  55 * lbzx RT,RA,RB
  56
  57 Pseudo-code:
  58
  59     b <- (RA|0)
  60     EA <- b + (RB)
  61     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  62
  63 Description:
  64
  65     Let the effective address (EA) be the sum
  66     (RA|0)+ (RB). The byte in storage addressed by EA is
  67     loaded into RT[56:63] . RT[0:55] are set to 0.
  68
  69 Special Registers Altered:
  70
  71     None
  72
  73 # Load Byte and Zero with Update
  74
  75 D-Form
  76
  77 * lbzu RT,D(RA)
  78
  79 Pseudo-code:
  80
  81     EA <- (RA) + EXTS(D)
  82     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  83     RA <- EA
  84
  85 Description:
  86
  87     Let the effective address (EA) be the sum (RA)+ D. The
  88     byte in storage addressed by EA is loaded into RT[56:63].
  89     RT[0:55] are set to 0.
  90
  91     EA is placed into register RA.
  92
  93     If RA=0 or RA=RT, the instruction form is invalid.
  94
  95 Special Registers Altered:
  96
  97     None
  98
  99 # Load Byte and Zero with Update Indexed
 100
 101 X-Form
 102
 103 * lbzux RT,RA,RB
 104
 105 Pseudo-code:
 106
 107     EA <- (RA) + (RB)
 108     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
 109     RA <- EA
 110
 111 Description:
 112
 113     Let the effective address (EA) be the sum (RA)+ (RB).
 114     The byte in storage addressed by EA is loaded into
 115     RT[56:63]. RT[0:55] are set to 0.
 116
 117     EA is placed into register RA.
 118
 119     If RA=0 or RA=RT, the instruction form is invalid.
 120
 121 Special Registers Altered:
 122
 123     None
 124
 125 # Load Halfword and Zero
 126
 127 D-Form
 128
 129 * lhz RT,D(RA)
 130
 131 Pseudo-code:
 132
 133     b <- (RA|0)
 134     EA <- b + EXTS(D)
 135     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 136
 137 Description:
 138
 139     Let the effective address (EA) be the sum (RA|0)+ D.
 140     The halfword in storage addressed by EA is loaded into
 141     RT[48:63]. RT[0:47] are set to 0.
 142
 143 Special Registers Altered:
 144
 145     None
 146
 147 # Load Halfword and Zero Indexed
 148
 149 X-Form
 150
 151 * lhzx RT,RA,RB
 152
 153 Pseudo-code:
 154
 155     b <- (RA|0)
 156     EA <- b + (RB)
 157     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 158
 159 Special Registers Altered:
 160
 161     None
 162
 163 # Load Halfword and Zero with Update
 164
 165 D-Form
 166
 167 * lhzu RT,D(RA)
 168
 169 Pseudo-code:
 170
 171     EA <- (RA) + EXTS(D)
 172     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 173     RA <- EA
 174
 175 Description:
 176
 177     Let the effective address (EA) be the sum (RA)+ D. The
 178     halfword in storage addressed by EA is loaded into
 179     RT[48:63]. RT[0:47] are set to 0.
 180
 181     EA is placed into register RA.
 182
 183     If RA=0 or RA=RT, the instruction form is invalid.
 184
 185 Special Registers Altered:
 186
 187     None
 188
 189 # Load Halfword and Zero with Update Indexed
 190
 191 X-Form
 192
 193 * lhzux RT,RA,RB
 194
 195 Pseudo-code:
 196
 197     EA <- (RA) + (RB)
 198     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 199     RA <- EA
 200
 201 Description:
 202
 203     Let the effective address (EA) be the sum (RA)+ (RB).
 204     The halfword in storage addressed by EA is loaded into
 205     RT[48:63]. RT[0:47] are set to 0.
 206
 207     EA is placed into register RA.
 208
 209     If RA=0 or RA=RT, the instruction form is invalid.
 210
 211 Special Registers Altered:
 212
 213     None
 214
 215 # Load Halfword Algebraic
 216
 217 D-Form
 218
 219 * lha RT,D(RA)
 220
 221 Pseudo-code:
 222
 223     b <- (RA|0)
 224     EA <- b + EXTS(D)
 225     RT <- EXTS(MEM(EA, 2))
 226
 227 Special Registers Altered:
 228
 229     None
 230
 231 # Load Halfword Algebraic Indexed
 232
 233 X-Form
 234
 235 * lhax RT,RA,RB
 236
 237 Pseudo-code:
 238
 239     b <- (RA|0)
 240     EA <- b + (RB)
 241     RT <- EXTS(MEM(EA, 2))
 242
 243 Special Registers Altered:
 244
 245     None
 246
 247 # Load Halfword Algebraic with Update
 248
 249 D-Form
 250
 251 * lhau RT,D(RA)
 252
 253 Pseudo-code:
 254
 255     EA <- (RA) + EXTS(D)
 256     RT <- EXTS(MEM(EA, 2))
 257     RA <- EA
 258
 259 Description:
 260
 261     Let the effective address (EA) be the sum (RA)+ D. The
 262     halfword in storage addressed by EA is loaded into
 263     RT[48:63]. RT[0:47] are filled with a copy of bit 0 of the
 264     loaded halfword.
 265
 266     EA is placed into register RA.
 267
 268     If RA=0 or RA=RT, the instruction form is invalid.
 269
 270 Special Registers Altered:
 271
 272     None
 273
 274 # Load Halfword Algebraic with Update Indexed
 275
 276 X-Form
 277
 278 * lhaux RT,RA,RB
 279
 280 Pseudo-code:
 281
 282     EA <- (RA) + (RB)
 283     RT <- EXTS(MEM(EA, 2))
 284     RA <- EA
 285
 286 Description:
 287
 288     Let the effective address (EA) be the sum (RA)+ (RB).
 289     The halfword in storage addressed by EA is loaded into
 290     RT48:63. RT 0:47 are filled with a copy of bit 0 of the
 291     loaded halfword.
 292
 293     EA is placed into register RA.
 294
 295     If RA=0 or RA=RT, the instruction form is invalid.
 296
 297 Special Registers Altered:
 298
 299     None
 300
 301 # Load Word and Zero
 302
 303 D-Form
 304
 305 * lwz RT,D(RA)
 306
 307 Pseudo-code:
 308
 309     b <- (RA|0)
 310     EA <- b + EXTS(D)
 311     RT <- [0] * 32 || MEM(EA, 4)
 312
 313 Special Registers Altered:
 314
 315     None
 316
 317 # Load Word and Zero Indexed
 318
 319 X-Form
 320
 321 * lwzx RT,RA,RB
 322
 323 Pseudo-code:
 324
 325     b <- (RA|0)
 326     EA <- b + (RB)
 327     RT <- [0] * 32 || MEM(EA, 4)
 328
 329 Special Registers Altered:
 330
 331     None
 332
 333 # Load Word and Zero with Update
 334
 335 D-Form
 336
 337 * lwzu RT,D(RA)
 338
 339 Pseudo-code:
 340
 341     EA <- (RA) + EXTS(D)
 342     RT <- [0]*32 || MEM(EA, 4)
 343     RA <- EA
 344
 345 Special Registers Altered:
 346
 347     None
 348
 349 # Load Word and Zero with Update Indexed
 350
 351 X-Form
 352
 353 * lwzux RT,RA,RB
 354
 355 Pseudo-code:
 356
 357     EA <- (RA) + (RB)
 358     RT <- [0] * 32 || MEM(EA, 4)
 359     RA <- EA
 360
 361 Special Registers Altered:
 362
 363     None
 364
 365 # Load Word Algebraic
 366
 367 DS-Form
 368
 369 * lwa RT,DS(RA)
 370
 371 Pseudo-code:
 372
 373     b <- (RA|0)
 374     EA <- b + EXTS(DS || 0b00)
 375     RT <- EXTS(MEM(EA, 4))
 376
 377 Special Registers Altered:
 378
 379     None
 380
 381 # Load Word Algebraic Indexed
 382
 383 X-Form
 384
 385 * lwax RT,RA,RB
 386
 387 Pseudo-code:
 388
 389     b <- (RA|0)
 390     EA <- b + (RB)
 391     RT <- EXTS(MEM(EA, 4))
 392
 393 Special Registers Altered:
 394
 395     None
 396
 397 # Load Word Algebraic with Update Indexed
 398
 399 X-Form
 400
 401 * lwaux RT,RA,RB
 402
 403 Pseudo-code:
 404
 405     EA <- (RA) + (RB)
 406     RT <- EXTS(MEM(EA, 4))
 407     RA <- EA
 408
 409 Special Registers Altered:
 410
 411     None
 412
 413 # Load Doubleword
 414
 415 DS-Form
 416
 417 * ld RT,DS(RA)
 418
 419 Pseudo-code:
 420
 421     b <- (RA|0)
 422     EA <- b + EXTS(DS || 0b00)
 423     RT <- MEM(EA, 8)
 424
 425 Special Registers Altered:
 426
 427     None
 428
 429 # Load Doubleword Indexed
 430
 431 X-Form
 432
 433 * ldx RT,RA,RB
 434
 435 Pseudo-code:
 436
 437     b <- (RA|0)
 438     EA <- b + (RB)
 439     RT <- MEM(EA, 8)
 440
 441 Special Registers Altered:
 442
 443     None
 444
 445 # Load Doubleword with Update Indexed
 446
 447 DS-Form
 448
 449 * ldu RT,DS(RA)
 450
 451 Pseudo-code:
 452
 453     EA <- (RA) + EXTS(DS || 0b00)
 454     RT <- MEM(EA, 8)
 455     RA <- EA
 456
 457 Special Registers Altered:
 458
 459     None
 460
 461 # Load Doubleword with Update Indexed
 462
 463 X-Form
 464
 465 * ldux RT,RA,RB
 466
 467 Pseudo-code:
 468
 469     EA <- (RA) + (RB)
 470     RT <- MEM(EA, 8)
 471     RA <- EA
 472
 473 Special Registers Altered:
 474
 475     None
 476
 477 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
 478
 479 <!-- The contents of register RS are stored into the byte, halfword, word, or -->
 480 <!-- doubleword in storage addressed by EA. -->
 481
 482 <!-- Many of the Store instructions have an “update” form, in which register RA is -->
 483 <!-- updated with the effective address. For these forms, the following rules apply. -->
 484
 485 <!-- If RA!=0, the effective address is placed into register RA. -->
 486
 487 <!-- If RS=RA, the contents of register RS are copied to the target storage element -->
 488 <!-- and then EA is placed into RA (RS). -->
 489
 490 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
 491
 492 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
 493
 494 <!-- For lq, the quadword in storage addressed by EA is loaded into an even-odd pair -->
 495 <!-- of GPRs as follows. In Big-Endian mode, the even-numbered GPR is loaded with -->
 496 <!-- the doubleword from storage addressed by EA and the odd-numbered GPR is loaded -->
 497 <!-- with the doubleword addressed by EA+8. In Little-Endian mode, the even-numbered -->
 498 <!-- GPR is loaded with the byte-reversed doubleword from storage addressed by EA+8 -->
 499 <!-- and the odd-numbered GPR is loaded with the byte-reversed doubleword addressed -->
 500 <!-- by EA. -->
 501
 502 # Load Quadword
 503
 504 DQ-Form
 505
 506 * lq RTp,DQ(RA)
 507
 508 Pseudo-code:
 509
 510     b <- (RA|0)
 511     EA <- b + EXTS(DQ || 0b0000)
 512     RTp <- MEM(EA, 16)
 513
 514 Special Registers Altered:
 515
 516     None
 517
 518 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
 519
 520 # Load Halfword Byte-Reverse Indexed
 521
 522 X-Form
 523
 524 * lhbrx RT,RA,RB
 525
 526 Pseudo-code:
 527
 528     b <- (RA|0)
 529     EA <- b + (RB)
 530     load_data <- MEM(EA, 2)
 531     RT <- [0]*48 || load_data[8:15] || load_data[0:7]
 532
 533 Special Registers Altered:
 534
 535     None
 536
 537 # Load Word Byte-Reverse Indexed
 538
 539 X-Form
 540
 541 * lwbrx RT,RA,RB
 542
 543 Pseudo-code:
 544
 545     b <- (RA|0)
 546     EA <- b + (RB)
 547     load_data <- MEM(EA, 4)
 548     RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
 549                     || load_data[8:15]  || load_data[0:7])
 550
 551 Special Registers Altered:
 552
 553     None
 554
 555
 556 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
 557
 558 # Load Doubleword Byte-Reverse Indexed
 559
 560 X-Form
 561
 562 * ldbrx RT,RA,RB
 563
 564 Pseudo-code:
 565
 566     b <- (RA|0)
 567     EA <- b + (RB)
 568     load_data <- MEM(EA, 8)
 569     RT <- (load_data[56:63] || load_data[48:55]
 570         || load_data[40:47] || load_data[32:39]
 571         || load_data[24:31] || load_data[16:23]
 572         || load_data[8:15]  || load_data[0:7])
 573
 574 Special Registers Altered:
 575
 576     None
 577
 578 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
 579
 580 # Load Multiple Word
 581
 582 DQ-Form
 583
 584 * lmw RT,D(RA)
 585
 586 Pseudo-code:
 587
 588     b <- (RA|0)
 589     EA <- b + EXTS(D)
 590     r <- RT[0:63]
 591     do while r <=  31
 592         GPR(r) <- [0]*32 || MEM(EA, 4)
 593         r <- r + 1
 594         EA <- EA + 4
 595
 596 Special Registers Altered:
 597
 598     None
 599