openpower/isa/fixedload.mdwn

   1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
   2
   3 <!-- This defines instructions that load from RAM to a register -->
   4
   5 <!-- Note that these pages also define equivalent store instructions, -->
   6 <!-- these are described in fixedstore.mdwn -->
   7
   8 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
   9 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
  10 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
  11 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
  12 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
  13 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
  14 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
  15
  16
  17
  18 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
  19
  20 <!-- The byte, halfword, word, or doubleword in storage addressed by EA is loaded -->
  21 <!-- into register RT. -->
  22
  23 <!-- Many of the Load instructions have an “update” form, in which register RA is -->
  24 <!-- updated with the effective address. For these forms, if RA!=0 and RA!=RT, the -->
  25 <!-- effective address is placed into register RA and the storage element (byte, -->
  26 <!-- halfword, word, or doubleword) addressed by EA is loaded into RT. -->
  27
  28
  29 # Load Byte and Zero
  30
  31 D-Form
  32
  33 * lbz RT,D(RA)
  34
  35 Pseudo-code:
  36
  37     b <- (RA|0)
  38     EA <- b + EXTS(D)
  39     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  40
  41 Description:
  42
  43 Let the effective address (EA) be the sum (RA|0)+ D.
  44 The byte in storage addressed by EA is loaded into
  45 RT[56:63]. RT[0:55] are set to 0.
  46
  47 Special Registers Altered:
  48
  49     None
  50
  51 # Load Byte and Zero Indexed
  52
  53 X-Form
  54
  55 * lbzx RT,RA,RB
  56
  57 Pseudo-code:
  58
  59     b <- (RA|0)
  60     EA <- b + (RB)
  61     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  62
  63 Special Registers Altered:
  64
  65     None
  66
  67 # Load Byte and Zero with Update
  68
  69 D-Form
  70
  71 * lbzu RT,D(RA)
  72
  73 Pseudo-code:
  74
  75     EA <- (RA) + EXTS(D)
  76     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  77     RA <- EA
  78
  79 Description:
  80
  81     Let the effective address (EA) be the sum (RA)+ D. The
  82     byte in storage addressed by EA is loaded into RT[56:63].
  83     RT[0:55] are set to 0.
  84
  85     EA is placed into register RA.
  86
  87     If RA=0 or RA=RT, the instruction form is invalid.
  88
  89 Special Registers Altered:
  90
  91     None
  92
  93 # Load Byte and Zero with Update Indexed
  94
  95 X-Form
  96
  97 * lbzux RT,RA,RB
  98
  99 Pseudo-code:
 100
 101     EA <- (RA) + (RB)
 102     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
 103     RA <- EA
 104
 105 Description:
 106
 107     Let the effective address (EA) be the sum (RA)+ (RB).
 108     The byte in storage addressed by EA is loaded into
 109     RT[56:63]. RT[0:55] are set to 0.
 110
 111     EA is placed into register RA.
 112
 113     If RA=0 or RA=RT, the instruction form is invalid.
 114
 115 Special Registers Altered:
 116
 117     None
 118
 119 # Load Halfword and Zero
 120
 121 D-Form
 122
 123 * lhz RT,D(RA)
 124
 125 Pseudo-code:
 126
 127     b <- (RA|0)
 128     EA <- b + EXTS(D)
 129     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 130
 131 Special Registers Altered:
 132
 133     None
 134
 135 # Load Halfword and Zero Indexed
 136
 137 X-Form
 138
 139 * lhzx RT,RA,RB
 140
 141 Pseudo-code:
 142
 143     b <- (RA|0)
 144     EA <- b + (RB)
 145     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 146
 147 Special Registers Altered:
 148
 149     None
 150
 151 # Load Halfword and Zero with Update
 152
 153 D-Form
 154
 155 * lhzu RT,D(RA)
 156
 157 Pseudo-code:
 158
 159     EA <- (RA) + EXTS(D)
 160     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 161     RA <- EA
 162
 163 Description:Let the effective address (EA) be the sum (RA)+ D. The
 164 halfword in storage addressed by EA is loaded into
 165 RT48:63. RT 0:47 are set to 0.
 166 EA is placed into register RA.
 167 If RA=0 or RA=RT, the instruction form is invalid.
 168
 169 Special Registers Altered:
 170
 171     None
 172
 173 # Load Halfword and Zero with Update Indexed
 174
 175 X-Form
 176
 177 * lhzux RT,RA,RB
 178
 179 Pseudo-code:
 180
 181     EA <- (RA) + (RB)
 182     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 183     RA <- EA
 184
 185 Special Registers Altered:
 186
 187     None
 188
 189 # Load Halfword Algebraic
 190
 191 D-Form
 192
 193 * lha RT,D(RA)
 194
 195 Pseudo-code:
 196
 197     b <- (RA|0)
 198     EA <- b + EXTS(D)
 199     RT <- EXTS(MEM(EA, 2))
 200
 201 Special Registers Altered:
 202
 203     None
 204
 205 # Load Halfword Algebraic Indexed
 206
 207 X-Form
 208
 209 * lhax RT,RA,RB
 210
 211 Pseudo-code:
 212
 213     b <- (RA|0)
 214     EA <- b + (RB)
 215     RT <- EXTS(MEM(EA, 2))
 216
 217 Special Registers Altered:
 218
 219     None
 220
 221 # Load Halfword Algebraic with Update
 222
 223 D-Form
 224
 225 * lhau RT,D(RA)
 226
 227 Pseudo-code:
 228
 229     EA <- (RA) + EXTS(D)
 230     RT <- EXTS(MEM(EA, 2))
 231     RA <- EA
 232
 233 Special Registers Altered:
 234
 235     None
 236
 237 # Load Halfword Algebraic with Update Indexed
 238
 239 X-Form
 240
 241 * lhaux RT,RA,RB
 242
 243 Pseudo-code:
 244
 245     EA <- (RA) + (RB)
 246     RT <- EXTS(MEM(EA, 2))
 247     RA <- EA
 248
 249 Special Registers Altered:
 250
 251     None
 252
 253 # Load Word and Zero
 254
 255 D-Form
 256
 257 * lwz RT,D(RA)
 258
 259 Pseudo-code:
 260
 261     b <- (RA|0)
 262     EA <- b + EXTS(D)
 263     RT <- [0] * 32 || MEM(EA, 4)
 264
 265 Special Registers Altered:
 266
 267     None
 268
 269 # Load Word and Zero Indexed
 270
 271 X-Form
 272
 273 * lwzx RT,RA,RB
 274
 275 Pseudo-code:
 276
 277     b <- (RA|0)
 278     EA <- b + (RB)
 279     RT <- [0] * 32 || MEM(EA, 4)
 280
 281 Special Registers Altered:
 282
 283     None
 284
 285 # Load Word and Zero with Update
 286
 287 D-Form
 288
 289 * lwzu RT,D(RA)
 290
 291 Pseudo-code:
 292
 293     EA <- (RA) + EXTS(D)
 294     RT <- [0]*32 || MEM(EA, 4)
 295     RA <- EA
 296
 297 Special Registers Altered:
 298
 299     None
 300
 301 # Load Word and Zero with Update Indexed
 302
 303 X-Form
 304
 305 * lwzux RT,RA,RB
 306
 307 Pseudo-code:
 308
 309     EA <- (RA) + (RB)
 310     RT <- [0] * 32 || MEM(EA, 4)
 311     RA <- EA
 312
 313 Special Registers Altered:
 314
 315     None
 316
 317 # Load Word Algebraic
 318
 319 DS-Form
 320
 321 * lwa RT,DS(RA)
 322
 323 Pseudo-code:
 324
 325     b <- (RA|0)
 326     EA <- b + EXTS(DS || 0b00)
 327     RT <- EXTS(MEM(EA, 4))
 328
 329 Special Registers Altered:
 330
 331     None
 332
 333 # Load Word Algebraic Indexed
 334
 335 X-Form
 336
 337 * lwax RT,RA,RB
 338
 339 Pseudo-code:
 340
 341     b <- (RA|0)
 342     EA <- b + (RB)
 343     RT <- EXTS(MEM(EA, 4))
 344
 345 Special Registers Altered:
 346
 347     None
 348
 349 # Load Word Algebraic with Update Indexed
 350
 351 X-Form
 352
 353 * lwaux RT,RA,RB
 354
 355 Pseudo-code:
 356
 357     EA <- (RA) + (RB)
 358     RT <- EXTS(MEM(EA, 4))
 359     RA <- EA
 360
 361 Special Registers Altered:
 362
 363     None
 364
 365 # Load Doubleword
 366
 367 DS-Form
 368
 369 * ld RT,DS(RA)
 370
 371 Pseudo-code:
 372
 373     b <- (RA|0)
 374     EA <- b + EXTS(DS || 0b00)
 375     RT <- MEM(EA, 8)
 376
 377 Special Registers Altered:
 378
 379     None
 380
 381 # Load Doubleword Indexed
 382
 383 X-Form
 384
 385 * ldx RT,RA,RB
 386
 387 Pseudo-code:
 388
 389     b <- (RA|0)
 390     EA <- b + (RB)
 391     RT <- MEM(EA, 8)
 392
 393 Special Registers Altered:
 394
 395     None
 396
 397 # Load Doubleword with Update Indexed
 398
 399 DS-Form
 400
 401 * ldu RT,DS(RA)
 402
 403 Pseudo-code:
 404
 405     EA <- (RA) + EXTS(DS || 0b00)
 406     RT <- MEM(EA, 8)
 407     RA <- EA
 408
 409 Special Registers Altered:
 410
 411     None
 412
 413 # Load Doubleword with Update Indexed
 414
 415 X-Form
 416
 417 * ldux RT,RA,RB
 418
 419 Pseudo-code:
 420
 421     EA <- (RA) + (RB)
 422     RT <- MEM(EA, 8)
 423     RA <- EA
 424
 425 Special Registers Altered:
 426
 427     None
 428
 429 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
 430
 431 <!-- The contents of register RS are stored into the byte, halfword, word, or -->
 432 <!-- doubleword in storage addressed by EA. -->
 433
 434 <!-- Many of the Store instructions have an “update” form, in which register RA is -->
 435 <!-- updated with the effective address. For these forms, the following rules apply. -->
 436
 437 <!-- If RA!=0, the effective address is placed into register RA. -->
 438
 439 <!-- If RS=RA, the contents of register RS are copied to the target storage element -->
 440 <!-- and then EA is placed into RA (RS). -->
 441
 442 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
 443
 444 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
 445
 446 <!-- For lq, the quadword in storage addressed by EA is loaded into an even-odd pair -->
 447 <!-- of GPRs as follows. In Big-Endian mode, the even-numbered GPR is loaded with -->
 448 <!-- the doubleword from storage addressed by EA and the odd-numbered GPR is loaded -->
 449 <!-- with the doubleword addressed by EA+8. In Little-Endian mode, the even-numbered -->
 450 <!-- GPR is loaded with the byte-reversed doubleword from storage addressed by EA+8 -->
 451 <!-- and the odd-numbered GPR is loaded with the byte-reversed doubleword addressed -->
 452 <!-- by EA. -->
 453
 454 # Load Quadword
 455
 456 DQ-Form
 457
 458 * lq RTp,DQ(RA)
 459
 460 Pseudo-code:
 461
 462     b <- (RA|0)
 463     EA <- b + EXTS(DQ || 0b0000)
 464     RTp <- MEM(EA, 16)
 465
 466 Special Registers Altered:
 467
 468     None
 469
 470 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
 471
 472 # Load Halfword Byte-Reverse Indexed
 473
 474 X-Form
 475
 476 * lhbrx RT,RA,RB
 477
 478 Pseudo-code:
 479
 480     b <- (RA|0)
 481     EA <- b + (RB)
 482     load_data <- MEM(EA, 2)
 483     RT <- [0]*48 || load_data[8:15] || load_data[0:7]
 484
 485 Special Registers Altered:
 486
 487     None
 488
 489 # Load Word Byte-Reverse Indexed
 490
 491 X-Form
 492
 493 * lwbrx RT,RA,RB
 494
 495 Pseudo-code:
 496
 497     b <- (RA|0)
 498     EA <- b + (RB)
 499     load_data <- MEM(EA, 4)
 500     RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
 501                     || load_data[8:15]  || load_data[0:7])
 502
 503 Special Registers Altered:
 504
 505     None
 506
 507
 508 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
 509
 510 # Load Doubleword Byte-Reverse Indexed
 511
 512 X-Form
 513
 514 * ldbrx RT,RA,RB
 515
 516 Pseudo-code:
 517
 518     b <- (RA|0)
 519     EA <- b + (RB)
 520     load_data <- MEM(EA, 8)
 521     RT <- (load_data[56:63] || load_data[48:55]
 522         || load_data[40:47] || load_data[32:39]
 523         || load_data[24:31] || load_data[16:23]
 524         || load_data[8:15]  || load_data[0:7])
 525
 526 Special Registers Altered:
 527
 528     None
 529
 530 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
 531
 532 # Load Multiple Word
 533
 534 DQ-Form
 535
 536 * lmw RT,D(RA)
 537
 538 Pseudo-code:
 539
 540     b <- (RA|0)
 541     EA <- b + EXTS(D)
 542     r <- RT[0:63]
 543     do while r <=  31
 544         GPR(r) <- [0]*32 || MEM(EA, 4)
 545         r <- r + 1
 546         EA <- EA + 4
 547
 548 Special Registers Altered:
 549
 550     None
 551