1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
3 <!-- This defines instructions that load from RAM to a register -->
5 <!-- Note that these pages also define equivalent store instructions, -->
6 <!-- these are described in fixedstore.mdwn -->
8 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
9 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
10 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
11 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
12 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
13 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
14 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
18 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
20 <!-- The byte, halfword, word, or doubleword in storage addressed by EA is loaded -->
21 <!-- into register RT. -->
23 <!-- Many of the Load instructions have an “update” form, in which register RA is -->
24 <!-- updated with the effective address. For these forms, if RA!=0 and RA!=RT, the -->
25 <!-- effective address is placed into register RA and the storage element (byte, -->
26 <!-- halfword, word, or doubleword) addressed by EA is loaded into RT. -->
39 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
43 Let the effective address (EA) be the sum (RA|0)+ D.
44 The byte in storage addressed by EA is loaded into
45 RT[56:63]. RT[0:55] are set to 0.
47 Special Registers Altered:
51 # Load Byte and Zero Indexed
61 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
63 Special Registers Altered:
67 # Load Byte and Zero with Update
76 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
79 Description:Let the effective address (EA) be the sum (RA)+ D. The
80 byte in storage addressed by EA is loaded into RT 56:63.
82 EA is placed into register RA.
83 If RA=0 or RA=RT, the instruction form is invalid.
85 Special Registers Altered:
89 # Load Byte and Zero with Update Indexed
98 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
101 Description:Let the effective address (EA) be the sum (RA)+ (RB).
102 The byte in storage addressed by EA is loaded into
103 RT56:63. RT0:55 are set to 0.
104 EA is placed into register RA.
105 If RA=0 or RA=RT, the instruction form is invalid.
107 Special Registers Altered:
111 # Load Halfword and Zero
121 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
123 Special Registers Altered:
127 # Load Halfword and Zero Indexed
137 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
139 Special Registers Altered:
143 # Load Halfword and Zero with Update
152 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
155 Special Registers Altered:
159 # Load Halfword and Zero with Update Indexed
168 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
171 Special Registers Altered:
175 # Load Halfword Algebraic
185 RT <- EXTS(MEM(EA, 2))
187 Special Registers Altered:
191 # Load Halfword Algebraic Indexed
201 RT <- EXTS(MEM(EA, 2))
203 Special Registers Altered:
207 # Load Halfword Algebraic with Update
216 RT <- EXTS(MEM(EA, 2))
219 Special Registers Altered:
223 # Load Halfword Algebraic with Update Indexed
232 RT <- EXTS(MEM(EA, 2))
235 Special Registers Altered:
249 RT <- [0] * 32 || MEM(EA, 4)
251 Special Registers Altered:
255 # Load Word and Zero Indexed
265 RT <- [0] * 32 || MEM(EA, 4)
267 Special Registers Altered:
271 # Load Word and Zero with Update
280 RT <- [0]*32 || MEM(EA, 4)
283 Special Registers Altered:
287 # Load Word and Zero with Update Indexed
296 RT <- [0] * 32 || MEM(EA, 4)
299 Special Registers Altered:
303 # Load Word Algebraic
312 EA <- b + EXTS(DS || 0b00)
313 RT <- EXTS(MEM(EA, 4))
315 Special Registers Altered:
319 # Load Word Algebraic Indexed
329 RT <- EXTS(MEM(EA, 4))
331 Special Registers Altered:
335 # Load Word Algebraic with Update Indexed
344 RT <- EXTS(MEM(EA, 4))
347 Special Registers Altered:
360 EA <- b + EXTS(DS || 0b00)
363 Special Registers Altered:
367 # Load Doubleword Indexed
379 Special Registers Altered:
383 # Load Doubleword with Update Indexed
391 EA <- (RA) + EXTS(DS || 0b00)
395 Special Registers Altered:
399 # Load Doubleword with Update Indexed
411 Special Registers Altered:
415 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
417 <!-- The contents of register RS are stored into the byte, halfword, word, or -->
418 <!-- doubleword in storage addressed by EA. -->
420 <!-- Many of the Store instructions have an “update” form, in which register RA is -->
421 <!-- updated with the effective address. For these forms, the following rules apply. -->
423 <!-- If RA!=0, the effective address is placed into register RA. -->
425 <!-- If RS=RA, the contents of register RS are copied to the target storage element -->
426 <!-- and then EA is placed into RA (RS). -->
428 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
430 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
432 <!-- For lq, the quadword in storage addressed by EA is loaded into an even-odd pair -->
433 <!-- of GPRs as follows. In Big-Endian mode, the even-numbered GPR is loaded with -->
434 <!-- the doubleword from storage addressed by EA and the odd-numbered GPR is loaded -->
435 <!-- with the doubleword addressed by EA+8. In Little-Endian mode, the even-numbered -->
436 <!-- GPR is loaded with the byte-reversed doubleword from storage addressed by EA+8 -->
437 <!-- and the odd-numbered GPR is loaded with the byte-reversed doubleword addressed -->
449 EA <- b + EXTS(DQ || 0b0000)
452 Special Registers Altered:
456 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
458 # Load Halfword Byte-Reverse Indexed
468 load_data <- MEM(EA, 2)
469 RT <- [0]*48 || load_data[8:15] || load_data[0:7]
471 Special Registers Altered:
475 # Load Word Byte-Reverse Indexed
485 load_data <- MEM(EA, 4)
486 RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
487 || load_data[8:15] || load_data[0:7])
489 Special Registers Altered:
494 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
496 # Load Doubleword Byte-Reverse Indexed
506 load_data <- MEM(EA, 8)
507 RT <- (load_data[56:63] || load_data[48:55]
508 || load_data[40:47] || load_data[32:39]
509 || load_data[24:31] || load_data[16:23]
510 || load_data[8:15] || load_data[0:7])
512 Special Registers Altered:
516 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
530 GPR(r) <- [0]*32 || MEM(EA, 4)
534 Special Registers Altered: