openpower/isa/fixedload.mdwn

   1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
   2
   3 <!-- This defines instructions that load from RAM to a register -->
   4
   5 <!-- Note that these pages also define equivalent store instructions, -->
   6 <!-- these are described in fixedstore.mdwn -->
   7
   8 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
   9 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
  10 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
  11 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
  12 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
  13 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
  14 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
  15
  16
  17
  18 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
  19
  20 <!-- The byte, halfword, word, or doubleword in storage addressed by EA is loaded -->
  21 <!-- into register RT. -->
  22
  23 <!-- Many of the Load instructions have an “update” form, in which register RA is -->
  24 <!-- updated with the effective address. For these forms, if RA!=0 and RA!=RT, the -->
  25 <!-- effective address is placed into register RA and the storage element (byte, -->
  26 <!-- halfword, word, or doubleword) addressed by EA is loaded into RT. -->
  27
  28
  29 # Load Byte and Zero
  30
  31 D-Form
  32
  33 * lbz RT,D(RA)
  34
  35 Pseudo-code:
  36
  37     b <- (RA|0)
  38     EA <- b + EXTS(D)
  39     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  40
  41 Description:
  42
  43 Let the effective address (EA) be the sum (RA|0)+ D.
  44 The byte in storage addressed by EA is loaded into
  45 RT[56:63]. RT[0:55] are set to 0.
  46
  47 Special Registers Altered:
  48
  49     None
  50
  51 # Load Byte and Zero Indexed
  52
  53 X-Form
  54
  55 * lbzx RT,RA,RB
  56
  57 Pseudo-code:
  58
  59     b <- (RA|0)
  60     EA <- b + (RB)
  61     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  62
  63 Special Registers Altered:
  64
  65     None
  66
  67 # Load Byte and Zero with Update
  68
  69 D-Form
  70
  71 * lbzu RT,D(RA)
  72
  73 Pseudo-code:
  74
  75     EA <- (RA) + EXTS(D)
  76     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  77     RA <- EA
  78
  79 Description:
  80
  81 Let the effective address (EA) be the sum (RA)+ D. The
  82 byte in storage addressed by EA is loaded into RT[56:63].
  83 RT[0:55] are set to 0.
  84
  85 EA is placed into register RA.
  86
  87 If RA=0 or RA=RT, the instruction form is invalid.
  88
  89 Special Registers Altered:
  90
  91     None
  92
  93 # Load Byte and Zero with Update Indexed
  94
  95 X-Form
  96
  97 * lbzux RT,RA,RB
  98
  99 Pseudo-code:
 100
 101     EA <- (RA) + (RB)
 102     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
 103     RA <- EA
 104
 105 Description:Let the effective address (EA) be the sum (RA)+ (RB).
 106 The byte in storage addressed by EA is loaded into
 107 RT56:63. RT0:55 are set to 0.
 108 EA is placed into register RA.
 109 If RA=0 or RA=RT, the instruction form is invalid.
 110
 111 Special Registers Altered:
 112
 113     None
 114
 115 # Load Halfword and Zero
 116
 117 D-Form
 118
 119 * lhz RT,D(RA)
 120
 121 Pseudo-code:
 122
 123     b <- (RA|0)
 124     EA <- b + EXTS(D)
 125     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 126
 127 Special Registers Altered:
 128
 129     None
 130
 131 # Load Halfword and Zero Indexed
 132
 133 X-Form
 134
 135 * lhzx RT,RA,RB
 136
 137 Pseudo-code:
 138
 139     b <- (RA|0)
 140     EA <- b + (RB)
 141     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 142
 143 Special Registers Altered:
 144
 145     None
 146
 147 # Load Halfword and Zero with Update
 148
 149 D-Form
 150
 151 * lhzu RT,D(RA)
 152
 153 Pseudo-code:
 154
 155     EA <- (RA) + EXTS(D)
 156     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 157     RA <- EA
 158
 159 Description:Let the effective address (EA) be the sum (RA)+ D. The
 160 halfword in storage addressed by EA is loaded into
 161 RT48:63. RT 0:47 are set to 0.
 162 EA is placed into register RA.
 163 If RA=0 or RA=RT, the instruction form is invalid.
 164
 165 Special Registers Altered:
 166
 167     None
 168
 169 # Load Halfword and Zero with Update Indexed
 170
 171 X-Form
 172
 173 * lhzux RT,RA,RB
 174
 175 Pseudo-code:
 176
 177     EA <- (RA) + (RB)
 178     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 179     RA <- EA
 180
 181 Special Registers Altered:
 182
 183     None
 184
 185 # Load Halfword Algebraic
 186
 187 D-Form
 188
 189 * lha RT,D(RA)
 190
 191 Pseudo-code:
 192
 193     b <- (RA|0)
 194     EA <- b + EXTS(D)
 195     RT <- EXTS(MEM(EA, 2))
 196
 197 Special Registers Altered:
 198
 199     None
 200
 201 # Load Halfword Algebraic Indexed
 202
 203 X-Form
 204
 205 * lhax RT,RA,RB
 206
 207 Pseudo-code:
 208
 209     b <- (RA|0)
 210     EA <- b + (RB)
 211     RT <- EXTS(MEM(EA, 2))
 212
 213 Special Registers Altered:
 214
 215     None
 216
 217 # Load Halfword Algebraic with Update
 218
 219 D-Form
 220
 221 * lhau RT,D(RA)
 222
 223 Pseudo-code:
 224
 225     EA <- (RA) + EXTS(D)
 226     RT <- EXTS(MEM(EA, 2))
 227     RA <- EA
 228
 229 Special Registers Altered:
 230
 231     None
 232
 233 # Load Halfword Algebraic with Update Indexed
 234
 235 X-Form
 236
 237 * lhaux RT,RA,RB
 238
 239 Pseudo-code:
 240
 241     EA <- (RA) + (RB)
 242     RT <- EXTS(MEM(EA, 2))
 243     RA <- EA
 244
 245 Special Registers Altered:
 246
 247     None
 248
 249 # Load Word and Zero
 250
 251 D-Form
 252
 253 * lwz RT,D(RA)
 254
 255 Pseudo-code:
 256
 257     b <- (RA|0)
 258     EA <- b + EXTS(D)
 259     RT <- [0] * 32 || MEM(EA, 4)
 260
 261 Special Registers Altered:
 262
 263     None
 264
 265 # Load Word and Zero Indexed
 266
 267 X-Form
 268
 269 * lwzx RT,RA,RB
 270
 271 Pseudo-code:
 272
 273     b <- (RA|0)
 274     EA <- b + (RB)
 275     RT <- [0] * 32 || MEM(EA, 4)
 276
 277 Special Registers Altered:
 278
 279     None
 280
 281 # Load Word and Zero with Update
 282
 283 D-Form
 284
 285 * lwzu RT,D(RA)
 286
 287 Pseudo-code:
 288
 289     EA <- (RA) + EXTS(D)
 290     RT <- [0]*32 || MEM(EA, 4)
 291     RA <- EA
 292
 293 Special Registers Altered:
 294
 295     None
 296
 297 # Load Word and Zero with Update Indexed
 298
 299 X-Form
 300
 301 * lwzux RT,RA,RB
 302
 303 Pseudo-code:
 304
 305     EA <- (RA) + (RB)
 306     RT <- [0] * 32 || MEM(EA, 4)
 307     RA <- EA
 308
 309 Special Registers Altered:
 310
 311     None
 312
 313 # Load Word Algebraic
 314
 315 DS-Form
 316
 317 * lwa RT,DS(RA)
 318
 319 Pseudo-code:
 320
 321     b <- (RA|0)
 322     EA <- b + EXTS(DS || 0b00)
 323     RT <- EXTS(MEM(EA, 4))
 324
 325 Special Registers Altered:
 326
 327     None
 328
 329 # Load Word Algebraic Indexed
 330
 331 X-Form
 332
 333 * lwax RT,RA,RB
 334
 335 Pseudo-code:
 336
 337     b <- (RA|0)
 338     EA <- b + (RB)
 339     RT <- EXTS(MEM(EA, 4))
 340
 341 Special Registers Altered:
 342
 343     None
 344
 345 # Load Word Algebraic with Update Indexed
 346
 347 X-Form
 348
 349 * lwaux RT,RA,RB
 350
 351 Pseudo-code:
 352
 353     EA <- (RA) + (RB)
 354     RT <- EXTS(MEM(EA, 4))
 355     RA <- EA
 356
 357 Special Registers Altered:
 358
 359     None
 360
 361 # Load Doubleword
 362
 363 DS-Form
 364
 365 * ld RT,DS(RA)
 366
 367 Pseudo-code:
 368
 369     b <- (RA|0)
 370     EA <- b + EXTS(DS || 0b00)
 371     RT <- MEM(EA, 8)
 372
 373 Special Registers Altered:
 374
 375     None
 376
 377 # Load Doubleword Indexed
 378
 379 X-Form
 380
 381 * ldx RT,RA,RB
 382
 383 Pseudo-code:
 384
 385     b <- (RA|0)
 386     EA <- b + (RB)
 387     RT <- MEM(EA, 8)
 388
 389 Special Registers Altered:
 390
 391     None
 392
 393 # Load Doubleword with Update Indexed
 394
 395 DS-Form
 396
 397 * ldu RT,DS(RA)
 398
 399 Pseudo-code:
 400
 401     EA <- (RA) + EXTS(DS || 0b00)
 402     RT <- MEM(EA, 8)
 403     RA <- EA
 404
 405 Special Registers Altered:
 406
 407     None
 408
 409 # Load Doubleword with Update Indexed
 410
 411 X-Form
 412
 413 * ldux RT,RA,RB
 414
 415 Pseudo-code:
 416
 417     EA <- (RA) + (RB)
 418     RT <- MEM(EA, 8)
 419     RA <- EA
 420
 421 Special Registers Altered:
 422
 423     None
 424
 425 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
 426
 427 <!-- The contents of register RS are stored into the byte, halfword, word, or -->
 428 <!-- doubleword in storage addressed by EA. -->
 429
 430 <!-- Many of the Store instructions have an “update” form, in which register RA is -->
 431 <!-- updated with the effective address. For these forms, the following rules apply. -->
 432
 433 <!-- If RA!=0, the effective address is placed into register RA. -->
 434
 435 <!-- If RS=RA, the contents of register RS are copied to the target storage element -->
 436 <!-- and then EA is placed into RA (RS). -->
 437
 438 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
 439
 440 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
 441
 442 <!-- For lq, the quadword in storage addressed by EA is loaded into an even-odd pair -->
 443 <!-- of GPRs as follows. In Big-Endian mode, the even-numbered GPR is loaded with -->
 444 <!-- the doubleword from storage addressed by EA and the odd-numbered GPR is loaded -->
 445 <!-- with the doubleword addressed by EA+8. In Little-Endian mode, the even-numbered -->
 446 <!-- GPR is loaded with the byte-reversed doubleword from storage addressed by EA+8 -->
 447 <!-- and the odd-numbered GPR is loaded with the byte-reversed doubleword addressed -->
 448 <!-- by EA. -->
 449
 450 # Load Quadword
 451
 452 DQ-Form
 453
 454 * lq RTp,DQ(RA)
 455
 456 Pseudo-code:
 457
 458     b <- (RA|0)
 459     EA <- b + EXTS(DQ || 0b0000)
 460     RTp <- MEM(EA, 16)
 461
 462 Special Registers Altered:
 463
 464     None
 465
 466 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
 467
 468 # Load Halfword Byte-Reverse Indexed
 469
 470 X-Form
 471
 472 * lhbrx RT,RA,RB
 473
 474 Pseudo-code:
 475
 476     b <- (RA|0)
 477     EA <- b + (RB)
 478     load_data <- MEM(EA, 2)
 479     RT <- [0]*48 || load_data[8:15] || load_data[0:7]
 480
 481 Special Registers Altered:
 482
 483     None
 484
 485 # Load Word Byte-Reverse Indexed
 486
 487 X-Form
 488
 489 * lwbrx RT,RA,RB
 490
 491 Pseudo-code:
 492
 493     b <- (RA|0)
 494     EA <- b + (RB)
 495     load_data <- MEM(EA, 4)
 496     RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
 497                     || load_data[8:15]  || load_data[0:7])
 498
 499 Special Registers Altered:
 500
 501     None
 502
 503
 504 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
 505
 506 # Load Doubleword Byte-Reverse Indexed
 507
 508 X-Form
 509
 510 * ldbrx RT,RA,RB
 511
 512 Pseudo-code:
 513
 514     b <- (RA|0)
 515     EA <- b + (RB)
 516     load_data <- MEM(EA, 8)
 517     RT <- (load_data[56:63] || load_data[48:55]
 518         || load_data[40:47] || load_data[32:39]
 519         || load_data[24:31] || load_data[16:23]
 520         || load_data[8:15]  || load_data[0:7])
 521
 522 Special Registers Altered:
 523
 524     None
 525
 526 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
 527
 528 # Load Multiple Word
 529
 530 DQ-Form
 531
 532 * lmw RT,D(RA)
 533
 534 Pseudo-code:
 535
 536     b <- (RA|0)
 537     EA <- b + EXTS(D)
 538     r <- RT[0:63]
 539     do while r <=  31
 540         GPR(r) <- [0]*32 || MEM(EA, 4)
 541         r <- r + 1
 542         EA <- EA + 4
 543
 544 Special Registers Altered:
 545
 546     None
 547