openpower/isa/fixedload.mdwn

   1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
   2
   3 <!-- This defines instructions that load from RAM to a register -->
   4
   5 <!-- Note that these pages also define equivalent store instructions, -->
   6 <!-- these are described in fixedstore.mdwn -->
   7
   8 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
   9 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
  10 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
  11 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
  12 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
  13 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
  14 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
  15
  16
  17
  18 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
  19
  20 <!-- The byte, halfword, word, or doubleword in storage addressed by EA is loaded -->
  21 <!-- into register RT. -->
  22
  23 <!-- Many of the Load instructions have an “update” form, in which register RA is -->
  24 <!-- updated with the effective address. For these forms, if RA!=0 and RA!=RT, the -->
  25 <!-- effective address is placed into register RA and the storage element (byte, -->
  26 <!-- halfword, word, or doubleword) addressed by EA is loaded into RT. -->
  27
  28
  29 # Load Byte and Zero
  30
  31 D-Form
  32
  33 * lbz RT,D(RA)
  34
  35 Pseudo-code:
  36
  37     b <- (RA|0)
  38     EA <- b + EXTS(D)
  39     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  40
  41 Description:
  42
  43     Let the effective address (EA) be the sum (RA|0)+ D.
  44     The byte in storage addressed by EA is loaded into
  45     RT[56:63]. RT[0:55] are set to 0.
  46
  47 Special Registers Altered:
  48
  49     None
  50
  51 # Load Byte and Zero Indexed
  52
  53 X-Form
  54
  55 * lbzx RT,RA,RB
  56
  57 Pseudo-code:
  58
  59     b <- (RA|0)
  60     EA <- b + (RB)
  61     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  62
  63 Description:
  64
  65     Let the effective address (EA) be the sum
  66     (RA|0)+ (RB). The byte in storage addressed by EA is
  67     loaded into RT[56:63] . RT[0:55] are set to 0.
  68
  69 Special Registers Altered:
  70
  71     None
  72
  73 # Load Byte and Zero with Update
  74
  75 D-Form
  76
  77 * lbzu RT,D(RA)
  78
  79 Pseudo-code:
  80
  81     EA <- (RA) + EXTS(D)
  82     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  83     RA <- EA
  84
  85 Description:
  86
  87     Let the effective address (EA) be the sum (RA)+ D. The
  88     byte in storage addressed by EA is loaded into RT[56:63].
  89     RT[0:55] are set to 0.
  90
  91     EA is placed into register RA.
  92
  93     If RA=0 or RA=RT, the instruction form is invalid.
  94
  95 Special Registers Altered:
  96
  97     None
  98
  99 # Load Byte and Zero with Update Indexed
 100
 101 X-Form
 102
 103 * lbzux RT,RA,RB
 104
 105 Pseudo-code:
 106
 107     EA <- (RA) + (RB)
 108     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
 109     RA <- EA
 110
 111 Description:
 112
 113     Let the effective address (EA) be the sum (RA)+ (RB).
 114     The byte in storage addressed by EA is loaded into
 115     RT[56:63]. RT[0:55] are set to 0.
 116
 117     EA is placed into register RA.
 118
 119     If RA=0 or RA=RT, the instruction form is invalid.
 120
 121 Special Registers Altered:
 122
 123     None
 124
 125 # Load Halfword and Zero
 126
 127 D-Form
 128
 129 * lhz RT,D(RA)
 130
 131 Pseudo-code:
 132
 133     b <- (RA|0)
 134     EA <- b + EXTS(D)
 135     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 136
 137 Description:
 138
 139     Let the effective address (EA) be the sum (RA|0)+ D.
 140     The halfword in storage addressed by EA is loaded into
 141     RT[48:63]. RT[0:47] are set to 0.
 142
 143 Special Registers Altered:
 144
 145     None
 146
 147 # Load Halfword and Zero Indexed
 148
 149 X-Form
 150
 151 * lhzx RT,RA,RB
 152
 153 Pseudo-code:
 154
 155     b <- (RA|0)
 156     EA <- b + (RB)
 157     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 158
 159 Description:
 160
 161     Let the effective address (EA) be the sum
 162     (RA|0)+ (RB). The halfword in storage addressed by
 163     EA is loaded into RT 48:63. RT 0:47 are set to 0.
 164
 165 Special Registers Altered:
 166
 167     None
 168
 169 # Load Halfword and Zero with Update
 170
 171 D-Form
 172
 173 * lhzu RT,D(RA)
 174
 175 Pseudo-code:
 176
 177     EA <- (RA) + EXTS(D)
 178     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 179     RA <- EA
 180
 181 Description:
 182
 183     Let the effective address (EA) be the sum (RA)+ D. The
 184     halfword in storage addressed by EA is loaded into
 185     RT[48:63]. RT[0:47] are set to 0.
 186
 187     EA is placed into register RA.
 188
 189     If RA=0 or RA=RT, the instruction form is invalid.
 190
 191 Special Registers Altered:
 192
 193     None
 194
 195 # Load Halfword and Zero with Update Indexed
 196
 197 X-Form
 198
 199 * lhzux RT,RA,RB
 200
 201 Pseudo-code:
 202
 203     EA <- (RA) + (RB)
 204     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 205     RA <- EA
 206
 207 Description:
 208
 209     Let the effective address (EA) be the sum (RA)+ (RB).
 210     The halfword in storage addressed by EA is loaded into
 211     RT[48:63]. RT[0:47] are set to 0.
 212
 213     EA is placed into register RA.
 214
 215     If RA=0 or RA=RT, the instruction form is invalid.
 216
 217 Special Registers Altered:
 218
 219     None
 220
 221 # Load Halfword Algebraic
 222
 223 D-Form
 224
 225 * lha RT,D(RA)
 226
 227 Pseudo-code:
 228
 229     b <- (RA|0)
 230     EA <- b + EXTS(D)
 231     RT <- EXTS(MEM(EA, 2))
 232
 233 Description:
 234
 235     Let the effective address (EA) be the sum (RA|0)+ D.
 236     The halfword in storage addressed by EA is loaded into
 237     RT[48:63]. RT[0:47] are filled with a copy of bit 0 of the
 238     loaded halfword.
 239
 240 Special Registers Altered:
 241
 242     None
 243
 244 # Load Halfword Algebraic Indexed
 245
 246 X-Form
 247
 248 * lhax RT,RA,RB
 249
 250 Pseudo-code:
 251
 252     b <- (RA|0)
 253     EA <- b + (RB)
 254     RT <- EXTS(MEM(EA, 2))
 255
 256 Description:
 257
 258     Let the effective address (EA) be the sum
 259     (RA|0)+ (RB). The halfword in storage addressed by
 260     EA is loaded into RT[48:63] . RT[0:47] are filled with a copy
 261     of bit 0 of the loaded halfword.
 262
 263 Special Registers Altered:
 264
 265     None
 266
 267 # Load Halfword Algebraic with Update
 268
 269 D-Form
 270
 271 * lhau RT,D(RA)
 272
 273 Pseudo-code:
 274
 275     EA <- (RA) + EXTS(D)
 276     RT <- EXTS(MEM(EA, 2))
 277     RA <- EA
 278
 279 Description:
 280
 281     Let the effective address (EA) be the sum (RA)+ D. The
 282     halfword in storage addressed by EA is loaded into
 283     RT[48:63]. RT[0:47] are filled with a copy of bit 0 of the
 284     loaded halfword.
 285
 286     EA is placed into register RA.
 287
 288     If RA=0 or RA=RT, the instruction form is invalid.
 289
 290 Special Registers Altered:
 291
 292     None
 293
 294 # Load Halfword Algebraic with Update Indexed
 295
 296 X-Form
 297
 298 * lhaux RT,RA,RB
 299
 300 Pseudo-code:
 301
 302     EA <- (RA) + (RB)
 303     RT <- EXTS(MEM(EA, 2))
 304     RA <- EA
 305
 306 Description:
 307
 308     Let the effective address (EA) be the sum (RA)+ (RB).
 309     The halfword in storage addressed by EA is loaded into
 310     RT[48:63]. RT[0:47] are filled with a copy of bit 0 of the
 311     loaded halfword.
 312
 313     EA is placed into register RA.
 314
 315     If RA=0 or RA=RT, the instruction form is invalid.
 316
 317 Special Registers Altered:
 318
 319     None
 320
 321 # Load Word and Zero
 322
 323 D-Form
 324
 325 * lwz RT,D(RA)
 326
 327 Pseudo-code:
 328
 329     b <- (RA|0)
 330     EA <- b + EXTS(D)
 331     RT <- [0] * 32 || MEM(EA, 4)
 332
 333 Description:
 334     Let the effective address (EA) be the sum (RA|0)+ D.
 335     The word in storage addressed by EA is loaded into
 336     RT[32:63]. RT[0:31] are set to 0.
 337
 338 Special Registers Altered:
 339
 340     None
 341
 342 # Load Word and Zero Indexed
 343
 344 X-Form
 345
 346 * lwzx RT,RA,RB
 347
 348 Pseudo-code:
 349
 350     b <- (RA|0)
 351     EA <- b + (RB)
 352     RT <- [0] * 32 || MEM(EA, 4)
 353
 354 Description:
 355
 356     Let the effective address (EA) be the sum
 357     (RA|0)+ (RB). The word in storage addressed by EA is
 358     loaded into RT[32:63] . RT[0:31] are set to 0.
 359
 360 Special Registers Altered:
 361
 362     None
 363
 364 # Load Word and Zero with Update
 365
 366 D-Form
 367
 368 * lwzu RT,D(RA)
 369
 370 Pseudo-code:
 371
 372     EA <- (RA) + EXTS(D)
 373     RT <- [0]*32 || MEM(EA, 4)
 374     RA <- EA
 375
 376 Special Registers Altered:
 377
 378     None
 379
 380 # Load Word and Zero with Update Indexed
 381
 382 X-Form
 383
 384 * lwzux RT,RA,RB
 385
 386 Pseudo-code:
 387
 388     EA <- (RA) + (RB)
 389     RT <- [0] * 32 || MEM(EA, 4)
 390     RA <- EA
 391
 392 Special Registers Altered:
 393
 394     None
 395
 396 # Load Word Algebraic
 397
 398 DS-Form
 399
 400 * lwa RT,DS(RA)
 401
 402 Pseudo-code:
 403
 404     b <- (RA|0)
 405     EA <- b + EXTS(DS || 0b00)
 406     RT <- EXTS(MEM(EA, 4))
 407
 408 Special Registers Altered:
 409
 410     None
 411
 412 # Load Word Algebraic Indexed
 413
 414 X-Form
 415
 416 * lwax RT,RA,RB
 417
 418 Pseudo-code:
 419
 420     b <- (RA|0)
 421     EA <- b + (RB)
 422     RT <- EXTS(MEM(EA, 4))
 423
 424 Special Registers Altered:
 425
 426     None
 427
 428 # Load Word Algebraic with Update Indexed
 429
 430 X-Form
 431
 432 * lwaux RT,RA,RB
 433
 434 Pseudo-code:
 435
 436     EA <- (RA) + (RB)
 437     RT <- EXTS(MEM(EA, 4))
 438     RA <- EA
 439
 440 Special Registers Altered:
 441
 442     None
 443
 444 # Load Doubleword
 445
 446 DS-Form
 447
 448 * ld RT,DS(RA)
 449
 450 Pseudo-code:
 451
 452     b <- (RA|0)
 453     EA <- b + EXTS(DS || 0b00)
 454     RT <- MEM(EA, 8)
 455
 456 Special Registers Altered:
 457
 458     None
 459
 460 # Load Doubleword Indexed
 461
 462 X-Form
 463
 464 * ldx RT,RA,RB
 465
 466 Pseudo-code:
 467
 468     b <- (RA|0)
 469     EA <- b + (RB)
 470     RT <- MEM(EA, 8)
 471
 472 Special Registers Altered:
 473
 474     None
 475
 476 # Load Doubleword with Update Indexed
 477
 478 DS-Form
 479
 480 * ldu RT,DS(RA)
 481
 482 Pseudo-code:
 483
 484     EA <- (RA) + EXTS(DS || 0b00)
 485     RT <- MEM(EA, 8)
 486     RA <- EA
 487
 488 Special Registers Altered:
 489
 490     None
 491
 492 # Load Doubleword with Update Indexed
 493
 494 X-Form
 495
 496 * ldux RT,RA,RB
 497
 498 Pseudo-code:
 499
 500     EA <- (RA) + (RB)
 501     RT <- MEM(EA, 8)
 502     RA <- EA
 503
 504 Special Registers Altered:
 505
 506     None
 507
 508 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
 509
 510 <!-- The contents of register RS are stored into the byte, halfword, word, or -->
 511 <!-- doubleword in storage addressed by EA. -->
 512
 513 <!-- Many of the Store instructions have an “update” form, in which register RA is -->
 514 <!-- updated with the effective address. For these forms, the following rules apply. -->
 515
 516 <!-- If RA!=0, the effective address is placed into register RA. -->
 517
 518 <!-- If RS=RA, the contents of register RS are copied to the target storage element -->
 519 <!-- and then EA is placed into RA (RS). -->
 520
 521 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
 522
 523 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
 524
 525 <!-- For lq, the quadword in storage addressed by EA is loaded into an even-odd pair -->
 526 <!-- of GPRs as follows. In Big-Endian mode, the even-numbered GPR is loaded with -->
 527 <!-- the doubleword from storage addressed by EA and the odd-numbered GPR is loaded -->
 528 <!-- with the doubleword addressed by EA+8. In Little-Endian mode, the even-numbered -->
 529 <!-- GPR is loaded with the byte-reversed doubleword from storage addressed by EA+8 -->
 530 <!-- and the odd-numbered GPR is loaded with the byte-reversed doubleword addressed -->
 531 <!-- by EA. -->
 532
 533 # Load Quadword
 534
 535 DQ-Form
 536
 537 * lq RTp,DQ(RA)
 538
 539 Pseudo-code:
 540
 541     b <- (RA|0)
 542     EA <- b + EXTS(DQ || 0b0000)
 543     RTp <- MEM(EA, 16)
 544
 545 Special Registers Altered:
 546
 547     None
 548
 549 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
 550
 551 # Load Halfword Byte-Reverse Indexed
 552
 553 X-Form
 554
 555 * lhbrx RT,RA,RB
 556
 557 Pseudo-code:
 558
 559     b <- (RA|0)
 560     EA <- b + (RB)
 561     load_data <- MEM(EA, 2)
 562     RT <- [0]*48 || load_data[8:15] || load_data[0:7]
 563
 564 Special Registers Altered:
 565
 566     None
 567
 568 # Load Word Byte-Reverse Indexed
 569
 570 X-Form
 571
 572 * lwbrx RT,RA,RB
 573
 574 Pseudo-code:
 575
 576     b <- (RA|0)
 577     EA <- b + (RB)
 578     load_data <- MEM(EA, 4)
 579     RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
 580                     || load_data[8:15]  || load_data[0:7])
 581
 582 Special Registers Altered:
 583
 584     None
 585
 586
 587 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
 588
 589 # Load Doubleword Byte-Reverse Indexed
 590
 591 X-Form
 592
 593 * ldbrx RT,RA,RB
 594
 595 Pseudo-code:
 596
 597     b <- (RA|0)
 598     EA <- b + (RB)
 599     load_data <- MEM(EA, 8)
 600     RT <- (load_data[56:63] || load_data[48:55]
 601         || load_data[40:47] || load_data[32:39]
 602         || load_data[24:31] || load_data[16:23]
 603         || load_data[8:15]  || load_data[0:7])
 604
 605 Special Registers Altered:
 606
 607     None
 608
 609 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
 610
 611 # Load Multiple Word
 612
 613 DQ-Form
 614
 615 * lmw RT,D(RA)
 616
 617 Pseudo-code:
 618
 619     b <- (RA|0)
 620     EA <- b + EXTS(D)
 621     r <- RT[0:63]
 622     do while r <=  31
 623         GPR(r) <- [0]*32 || MEM(EA, 4)
 624         r <- r + 1
 625         EA <- EA + 4
 626
 627 Special Registers Altered:
 628
 629     None
 630