openpower/isa/fixedload.mdwn

   1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
   2
   3 <!-- This defines instructions that load from RAM to a register -->
   4
   5 <!-- Note that these pages also define equivalent store instructions, -->
   6 <!-- these are described in fixedstore.mdwn -->
   7
   8 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
   9 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
  10 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
  11 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
  12 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
  13 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
  14 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
  15
  16
  17
  18 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
  19
  20 <!-- The byte, halfword, word, or doubleword in storage addressed by EA is loaded -->
  21 <!-- into register RT. -->
  22
  23 <!-- Many of the Load instructions have an “update” form, in which register RA is -->
  24 <!-- updated with the effective address. For these forms, if RA!=0 and RA!=RT, the -->
  25 <!-- effective address is placed into register RA and the storage element (byte, -->
  26 <!-- halfword, word, or doubleword) addressed by EA is loaded into RT. -->
  27
  28
  29 # Load Byte and Zero
  30
  31 D-Form
  32
  33 * lbz RT,D(RA)
  34
  35 Pseudo-code:
  36
  37     b <- (RA|0)
  38     EA <- b + EXTS(D)
  39     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  40
  41 Description:
  42
  43     Let the effective address (EA) be the sum (RA|0)+ D.
  44     The byte in storage addressed by EA is loaded into
  45     RT[56:63]. RT[0:55] are set to 0.
  46
  47 Special Registers Altered:
  48
  49     None
  50
  51 # Load Byte and Zero Indexed
  52
  53 X-Form
  54
  55 * lbzx RT,RA,RB
  56
  57 Pseudo-code:
  58
  59     b <- (RA|0)
  60     EA <- b + (RB)
  61     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  62
  63 Special Registers Altered:
  64
  65     None
  66
  67 # Load Byte and Zero with Update
  68
  69 D-Form
  70
  71 * lbzu RT,D(RA)
  72
  73 Pseudo-code:
  74
  75     EA <- (RA) + EXTS(D)
  76     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  77     RA <- EA
  78
  79 Description:
  80
  81     Let the effective address (EA) be the sum (RA)+ D. The
  82     byte in storage addressed by EA is loaded into RT[56:63].
  83     RT[0:55] are set to 0.
  84
  85     EA is placed into register RA.
  86
  87     If RA=0 or RA=RT, the instruction form is invalid.
  88
  89 Special Registers Altered:
  90
  91     None
  92
  93 # Load Byte and Zero with Update Indexed
  94
  95 X-Form
  96
  97 * lbzux RT,RA,RB
  98
  99 Pseudo-code:
 100
 101     EA <- (RA) + (RB)
 102     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
 103     RA <- EA
 104
 105 Description:
 106
 107     Let the effective address (EA) be the sum (RA)+ (RB).
 108     The byte in storage addressed by EA is loaded into
 109     RT[56:63]. RT[0:55] are set to 0.
 110
 111     EA is placed into register RA.
 112
 113     If RA=0 or RA=RT, the instruction form is invalid.
 114
 115 Special Registers Altered:
 116
 117     None
 118
 119 # Load Halfword and Zero
 120
 121 D-Form
 122
 123 * lhz RT,D(RA)
 124
 125 Pseudo-code:
 126
 127     b <- (RA|0)
 128     EA <- b + EXTS(D)
 129     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 130
 131 Special Registers Altered:
 132
 133     None
 134
 135 # Load Halfword and Zero Indexed
 136
 137 X-Form
 138
 139 * lhzx RT,RA,RB
 140
 141 Pseudo-code:
 142
 143     b <- (RA|0)
 144     EA <- b + (RB)
 145     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 146
 147 Special Registers Altered:
 148
 149     None
 150
 151 # Load Halfword and Zero with Update
 152
 153 D-Form
 154
 155 * lhzu RT,D(RA)
 156
 157 Pseudo-code:
 158
 159     EA <- (RA) + EXTS(D)
 160     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 161     RA <- EA
 162
 163 Description:
 164
 165     Let the effective address (EA) be the sum (RA)+ D. The
 166     halfword in storage addressed by EA is loaded into
 167     RT[48:63]. RT[0:47] are set to 0.
 168
 169     EA is placed into register RA.
 170
 171     If RA=0 or RA=RT, the instruction form is invalid.
 172
 173 Special Registers Altered:
 174
 175     None
 176
 177 # Load Halfword and Zero with Update Indexed
 178
 179 X-Form
 180
 181 * lhzux RT,RA,RB
 182
 183 Pseudo-code:
 184
 185     EA <- (RA) + (RB)
 186     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 187     RA <- EA
 188
 189 Description:
 190
 191     Let the effective address (EA) be the sum (RA)+ (RB).
 192     The halfword in storage addressed by EA is loaded into
 193     RT[48:63]. RT[0:47] are set to 0.
 194
 195     EA is placed into register RA.
 196
 197     If RA=0 or RA=RT, the instruction form is invalid.
 198
 199 Special Registers Altered:
 200
 201     None
 202
 203 # Load Halfword Algebraic
 204
 205 D-Form
 206
 207 * lha RT,D(RA)
 208
 209 Pseudo-code:
 210
 211     b <- (RA|0)
 212     EA <- b + EXTS(D)
 213     RT <- EXTS(MEM(EA, 2))
 214
 215 Special Registers Altered:
 216
 217     None
 218
 219 # Load Halfword Algebraic Indexed
 220
 221 X-Form
 222
 223 * lhax RT,RA,RB
 224
 225 Pseudo-code:
 226
 227     b <- (RA|0)
 228     EA <- b + (RB)
 229     RT <- EXTS(MEM(EA, 2))
 230
 231 Special Registers Altered:
 232
 233     None
 234
 235 # Load Halfword Algebraic with Update
 236
 237 D-Form
 238
 239 * lhau RT,D(RA)
 240
 241 Pseudo-code:
 242
 243     EA <- (RA) + EXTS(D)
 244     RT <- EXTS(MEM(EA, 2))
 245     RA <- EA
 246
 247 Special Registers Altered:
 248
 249     None
 250
 251 # Load Halfword Algebraic with Update Indexed
 252
 253 X-Form
 254
 255 * lhaux RT,RA,RB
 256
 257 Pseudo-code:
 258
 259     EA <- (RA) + (RB)
 260     RT <- EXTS(MEM(EA, 2))
 261     RA <- EA
 262
 263 Special Registers Altered:
 264
 265     None
 266
 267 # Load Word and Zero
 268
 269 D-Form
 270
 271 * lwz RT,D(RA)
 272
 273 Pseudo-code:
 274
 275     b <- (RA|0)
 276     EA <- b + EXTS(D)
 277     RT <- [0] * 32 || MEM(EA, 4)
 278
 279 Special Registers Altered:
 280
 281     None
 282
 283 # Load Word and Zero Indexed
 284
 285 X-Form
 286
 287 * lwzx RT,RA,RB
 288
 289 Pseudo-code:
 290
 291     b <- (RA|0)
 292     EA <- b + (RB)
 293     RT <- [0] * 32 || MEM(EA, 4)
 294
 295 Special Registers Altered:
 296
 297     None
 298
 299 # Load Word and Zero with Update
 300
 301 D-Form
 302
 303 * lwzu RT,D(RA)
 304
 305 Pseudo-code:
 306
 307     EA <- (RA) + EXTS(D)
 308     RT <- [0]*32 || MEM(EA, 4)
 309     RA <- EA
 310
 311 Special Registers Altered:
 312
 313     None
 314
 315 # Load Word and Zero with Update Indexed
 316
 317 X-Form
 318
 319 * lwzux RT,RA,RB
 320
 321 Pseudo-code:
 322
 323     EA <- (RA) + (RB)
 324     RT <- [0] * 32 || MEM(EA, 4)
 325     RA <- EA
 326
 327 Special Registers Altered:
 328
 329     None
 330
 331 # Load Word Algebraic
 332
 333 DS-Form
 334
 335 * lwa RT,DS(RA)
 336
 337 Pseudo-code:
 338
 339     b <- (RA|0)
 340     EA <- b + EXTS(DS || 0b00)
 341     RT <- EXTS(MEM(EA, 4))
 342
 343 Special Registers Altered:
 344
 345     None
 346
 347 # Load Word Algebraic Indexed
 348
 349 X-Form
 350
 351 * lwax RT,RA,RB
 352
 353 Pseudo-code:
 354
 355     b <- (RA|0)
 356     EA <- b + (RB)
 357     RT <- EXTS(MEM(EA, 4))
 358
 359 Special Registers Altered:
 360
 361     None
 362
 363 # Load Word Algebraic with Update Indexed
 364
 365 X-Form
 366
 367 * lwaux RT,RA,RB
 368
 369 Pseudo-code:
 370
 371     EA <- (RA) + (RB)
 372     RT <- EXTS(MEM(EA, 4))
 373     RA <- EA
 374
 375 Special Registers Altered:
 376
 377     None
 378
 379 # Load Doubleword
 380
 381 DS-Form
 382
 383 * ld RT,DS(RA)
 384
 385 Pseudo-code:
 386
 387     b <- (RA|0)
 388     EA <- b + EXTS(DS || 0b00)
 389     RT <- MEM(EA, 8)
 390
 391 Special Registers Altered:
 392
 393     None
 394
 395 # Load Doubleword Indexed
 396
 397 X-Form
 398
 399 * ldx RT,RA,RB
 400
 401 Pseudo-code:
 402
 403     b <- (RA|0)
 404     EA <- b + (RB)
 405     RT <- MEM(EA, 8)
 406
 407 Special Registers Altered:
 408
 409     None
 410
 411 # Load Doubleword with Update Indexed
 412
 413 DS-Form
 414
 415 * ldu RT,DS(RA)
 416
 417 Pseudo-code:
 418
 419     EA <- (RA) + EXTS(DS || 0b00)
 420     RT <- MEM(EA, 8)
 421     RA <- EA
 422
 423 Special Registers Altered:
 424
 425     None
 426
 427 # Load Doubleword with Update Indexed
 428
 429 X-Form
 430
 431 * ldux RT,RA,RB
 432
 433 Pseudo-code:
 434
 435     EA <- (RA) + (RB)
 436     RT <- MEM(EA, 8)
 437     RA <- EA
 438
 439 Special Registers Altered:
 440
 441     None
 442
 443 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
 444
 445 <!-- The contents of register RS are stored into the byte, halfword, word, or -->
 446 <!-- doubleword in storage addressed by EA. -->
 447
 448 <!-- Many of the Store instructions have an “update” form, in which register RA is -->
 449 <!-- updated with the effective address. For these forms, the following rules apply. -->
 450
 451 <!-- If RA!=0, the effective address is placed into register RA. -->
 452
 453 <!-- If RS=RA, the contents of register RS are copied to the target storage element -->
 454 <!-- and then EA is placed into RA (RS). -->
 455
 456 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
 457
 458 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
 459
 460 <!-- For lq, the quadword in storage addressed by EA is loaded into an even-odd pair -->
 461 <!-- of GPRs as follows. In Big-Endian mode, the even-numbered GPR is loaded with -->
 462 <!-- the doubleword from storage addressed by EA and the odd-numbered GPR is loaded -->
 463 <!-- with the doubleword addressed by EA+8. In Little-Endian mode, the even-numbered -->
 464 <!-- GPR is loaded with the byte-reversed doubleword from storage addressed by EA+8 -->
 465 <!-- and the odd-numbered GPR is loaded with the byte-reversed doubleword addressed -->
 466 <!-- by EA. -->
 467
 468 # Load Quadword
 469
 470 DQ-Form
 471
 472 * lq RTp,DQ(RA)
 473
 474 Pseudo-code:
 475
 476     b <- (RA|0)
 477     EA <- b + EXTS(DQ || 0b0000)
 478     RTp <- MEM(EA, 16)
 479
 480 Special Registers Altered:
 481
 482     None
 483
 484 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
 485
 486 # Load Halfword Byte-Reverse Indexed
 487
 488 X-Form
 489
 490 * lhbrx RT,RA,RB
 491
 492 Pseudo-code:
 493
 494     b <- (RA|0)
 495     EA <- b + (RB)
 496     load_data <- MEM(EA, 2)
 497     RT <- [0]*48 || load_data[8:15] || load_data[0:7]
 498
 499 Special Registers Altered:
 500
 501     None
 502
 503 # Load Word Byte-Reverse Indexed
 504
 505 X-Form
 506
 507 * lwbrx RT,RA,RB
 508
 509 Pseudo-code:
 510
 511     b <- (RA|0)
 512     EA <- b + (RB)
 513     load_data <- MEM(EA, 4)
 514     RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
 515                     || load_data[8:15]  || load_data[0:7])
 516
 517 Special Registers Altered:
 518
 519     None
 520
 521
 522 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
 523
 524 # Load Doubleword Byte-Reverse Indexed
 525
 526 X-Form
 527
 528 * ldbrx RT,RA,RB
 529
 530 Pseudo-code:
 531
 532     b <- (RA|0)
 533     EA <- b + (RB)
 534     load_data <- MEM(EA, 8)
 535     RT <- (load_data[56:63] || load_data[48:55]
 536         || load_data[40:47] || load_data[32:39]
 537         || load_data[24:31] || load_data[16:23]
 538         || load_data[8:15]  || load_data[0:7])
 539
 540 Special Registers Altered:
 541
 542     None
 543
 544 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
 545
 546 # Load Multiple Word
 547
 548 DQ-Form
 549
 550 * lmw RT,D(RA)
 551
 552 Pseudo-code:
 553
 554     b <- (RA|0)
 555     EA <- b + EXTS(D)
 556     r <- RT[0:63]
 557     do while r <=  31
 558         GPR(r) <- [0]*32 || MEM(EA, 4)
 559         r <- r + 1
 560         EA <- EA + 4
 561
 562 Special Registers Altered:
 563
 564     None
 565